Put PHI/INLINEASM into the correct namespace.

[oota-llvm.git] / lib / Target / Target.td

diff --git a/lib/Target/Target.td b/lib/Target/Target.td
index 1466830431f7dcf9e02e868ca4f93e5cd35b7395..92179a5fafa5e8fc666d21ac41d7fb226c171bb0 100644 (file)
--- a/lib/Target/Target.td
+++ b/lib/Target/Target.td
@@ -12,42 +12,8 @@
 //
 //===----------------------------------------------------------------------===//
 
-
-//===----------------------------------------------------------------------===//
-//
-// Value types - These values correspond to the register types defined in the
-// ValueTypes.h file.  If you update anything here, you must update it there as
-// well!
-//
-class ValueType<int size, int value> {
-  string Namespace = "MVT";
-  int Size = size;
-  int Value = value;
-}
-
-def OtherVT: ValueType<0  ,  0>;   // "Other" value
-def i1     : ValueType<1  ,  1>;   // One bit boolean value
-def i8     : ValueType<8  ,  2>;   // 8-bit integer value
-def i16    : ValueType<16 ,  3>;   // 16-bit integer value
-def i32    : ValueType<32 ,  4>;   // 32-bit integer value
-def i64    : ValueType<64 ,  5>;   // 64-bit integer value
-def i128   : ValueType<128,  6>;   // 128-bit integer value
-def f32    : ValueType<32 ,  7>;   // 32-bit floating point value
-def f64    : ValueType<64 ,  8>;   // 64-bit floating point value
-def f80    : ValueType<80 ,  9>;   // 80-bit floating point value
-def f128   : ValueType<128, 10>;   // 128-bit floating point value
-def FlagVT : ValueType<0  , 11>;   // Condition code or machine flag
-def isVoid : ValueType<0  , 12>;   // Produces no value
-def Vector : ValueType<0  , 13>;   // Abstract vector value
-def v8i8   : ValueType<64 , 14>;   //  8 x i8  vector value
-def v4i16  : ValueType<64 , 15>;   //  4 x i16 vector value
-def v2i32  : ValueType<64 , 16>;   //  2 x i32 vector value
-def v16i8  : ValueType<128, 17>;   // 16 x i8  vector value
-def v8i16  : ValueType<128, 18>;   //  8 x i16 vector value
-def v4i32  : ValueType<128, 19>;   //  4 x i32 vector value
-def v2i64  : ValueType<128, 20>;   //  2 x i64 vector value
-def v4f32  : ValueType<128, 21>;   //  4 x f32 vector value
-def v2f64  : ValueType<128, 22>;   //  2 x f64 vector value
+// Include all information about LLVM intrinsics.
+include "llvm/Intrinsics.td"
 
 //===----------------------------------------------------------------------===//
 // Register file description - These classes are used to fill in the target
@@ -77,6 +43,13 @@ class Register<string n> {
   // registers.
   //
   list<Register> Aliases = [];
+  
+  // DwarfNumber - Number used internally by gcc/gdb to identify the register.
+  // These values can be determined by locating the <target>.h file in the
+  // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES.  The
+  // order of these names correspond to the enumeration used by gcc.  A value of
+  // -1 indicates that the gcc number is undefined.
+  int DwarfNumber = -1;
 }
 
 // RegisterGroup - This can be used to define instances of Register which
@@ -125,6 +98,20 @@ class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
 }
 
 
+//===----------------------------------------------------------------------===//
+// DwarfRegNum - This class provides a mapping of the llvm register enumeration
+// to the register numbering used by gcc and gdb.  These values are used by a
+// debug information writer (ex. DwarfWriter) to describe where values may be
+// located during execution.
+class DwarfRegNum<int N> {
+  // DwarfNumber - Number used internally by gcc/gdb to identify the register.
+  // These values can be determined by locating the <target>.h file in the
+  // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES.  The
+  // order of these names correspond to the enumeration used by gcc.  A value of
+  // -1 indicates that the gcc number is undefined.
+  int DwarfNumber = N;
+}
+
 //===----------------------------------------------------------------------===//
 // Pull in the common support for scheduling
 //
@@ -157,6 +144,9 @@ class Instruction {
   // code.
   list<Predicate> Predicates = [];
 
+  // Added complexity passed onto matching pattern.
+  int AddedComplexity  = 0;
+
   // These bits capture information about the high-level semantics of the
   // instruction.
   bit isReturn     = 0;     // Is this instruction a return instruction?
@@ -234,10 +224,12 @@ class InstrInfo {
 def PHI : Instruction {
   let OperandList = (ops variable_ops);
   let AsmString = "PHINODE";
+  let Namespace = "TargetInstrInfo";
 }
 def INLINEASM : Instruction {
   let OperandList = (ops variable_ops);
   let AsmString = "";
+  let Namespace = "TargetInstrInfo";
 }
 
 //===----------------------------------------------------------------------===//