//
//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-//
-// Value types - These values correspond to the register types defined in the
-// ValueTypes.h file. If you update anything here, you must update it there as
-// well!
-//
-class ValueType<int size, int value> {
- string Namespace = "MVT";
- int Size = size;
- int Value = value;
-}
-
-def OtherVT: ValueType<0 , 0>; // "Other" value
-def i1 : ValueType<1 , 1>; // One bit boolean value
-def i8 : ValueType<8 , 2>; // 8-bit integer value
-def i16 : ValueType<16 , 3>; // 16-bit integer value
-def i32 : ValueType<32 , 4>; // 32-bit integer value
-def i64 : ValueType<64 , 5>; // 64-bit integer value
-def i128 : ValueType<128, 5>; // 128-bit integer value
-def f32 : ValueType<32 , 7>; // 32-bit floating point value
-def f64 : ValueType<64 , 8>; // 64-bit floating point value
-def f80 : ValueType<80 , 9>; // 80-bit floating point value
-def f128 : ValueType<128, 10>; // 128-bit floating point value
-def FlagVT : ValueType<0 , 11>; // Condition code or machine flag
-def isVoid : ValueType<0 , 12>; // Produces no value
+// Include all information about LLVM intrinsics.
+include "llvm/Intrinsics.td"
//===----------------------------------------------------------------------===//
// Register file description - These classes are used to fill in the target
-// description classes in llvm/Target/MRegisterInfo.h
+// description classes.
+class RegisterClass; // Forward def
// Register - You should define one instance of this class for each register
// in the target machine. String n will become the "name" of the register.
-class RegisterBase<string n> {
+class Register<string n> {
string Namespace = "";
string Name = n;
// spilling the register. Like SpillSize, this should only be explicitly
// specified if the register is not in a register class.
int SpillAlignment = 0;
-}
-class Register<string n> : RegisterBase<n> {
- list<RegisterBase> Aliases = [];
+ // Aliases - A list of registers that this register overlaps with. A read or
+ // modification of this register can potentially read or modifie the aliased
+ // registers.
+ //
+ list<Register> Aliases = [];
+
+ // DwarfNumber - Number used internally by gcc/gdb to identify the register.
+ // These values can be determined by locating the <target>.h file in the
+ // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
+ // order of these names correspond to the enumeration used by gcc. A value of
+ // -1 indicates that the gcc number is undefined.
+ int DwarfNumber = -1;
}
// RegisterGroup - This can be used to define instances of Register which
// register classes. This also defines the default allocation order of
// registers by register allocators.
//
-class RegisterClass<string namespace, ValueType regType, int alignment,
+class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
list<Register> regList> {
string Namespace = namespace;
- // RegType - Specify the ValueType of the registers in this register class.
- // Note that all registers in a register class must have the same ValueType.
+ // RegType - Specify the list ValueType of the registers in this register
+ // class. Note that all registers in a register class must have the same
+ // ValueTypes. This is a list because some targets permit storing different
+ // types in same register, for example vector values with 128-bit total size,
+ // but different count/size of items, like SSE on x86.
//
- ValueType RegType = regType;
+ list<ValueType> RegTypes = regTypes;
+
+ // Size - Specify the spill size in bits of the registers. A default value of
+ // zero lets tablgen pick an appropriate size.
+ int Size = 0;
// Alignment - Specify the alignment required of the registers when they are
// stored or loaded to memory.
//
- int Size = RegType.Size;
int Alignment = alignment;
// MemberList - Specify which registers are in this class. If the
}
+//===----------------------------------------------------------------------===//
+// DwarfRegNum - This class provides a mapping of the llvm register enumeration
+// to the register numbering used by gcc and gdb. These values are used by a
+// debug information writer (ex. DwarfWriter) to describe where values may be
+// located during execution.
+class DwarfRegNum<int N> {
+ // DwarfNumber - Number used internally by gcc/gdb to identify the register.
+ // These values can be determined by locating the <target>.h file in the
+ // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
+ // order of these names correspond to the enumeration used by gcc. A value of
+ // -1 indicates that the gcc number is undefined.
+ int DwarfNumber = N;
+}
+
+//===----------------------------------------------------------------------===//
+// Pull in the common support for scheduling
+//
+include "TargetSchedule.td"
+
+class Predicate; // Forward def
+
//===----------------------------------------------------------------------===//
// Instruction set description - These classes correspond to the C++ classes in
// the Target/TargetInstrInfo.h file.
list<Register> Uses = []; // Default to using no non-operand registers
list<Register> Defs = []; // Default to modifying no non-operand registers
+ // Predicates - List of predicates which will be turned into isel matching
+ // code.
+ list<Predicate> Predicates = [];
+
+ // Added complexity passed onto matching pattern.
+ int AddedComplexity = 0;
+
// These bits capture information about the high-level semantics of the
// instruction.
bit isReturn = 0; // Is this instruction a return instruction?
bit isTerminator = 0; // Is this part of the terminator for a basic block?
bit hasDelaySlot = 0; // Does this instruction have an delay slot?
bit usesCustomDAGSchedInserter = 0; // Pseudo instr needing special help.
+ bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
+ bit noResults = 0; // Does this instruction produce no results?
+
+ InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
}
+/// Predicates - These are extra conditionals which are turned into instruction
+/// selector matching code. Currently each predicate is just a string.
+class Predicate<string cond> {
+ string CondString = cond;
+}
+
+class Requires<list<Predicate> preds> {
+ list<Predicate> Predicates = preds;
+}
/// ops definition - This is just a simple marker used to identify the operands
/// list for an instruction. This should be used like this:
/// of operands.
def variable_ops;
+/// ptr_rc definition - Mark this operand as being a pointer value whose
+/// register class is resolved dynamically via a callback to TargetInstrInfo.
+/// FIXME: We should probably change this to a class which contain a list of
+/// flags. But currently we have but one flag.
+def ptr_rc;
+
/// Operand Types - These provide the built-in operand types that may be used
/// by a target. Targets can optionally provide their own operand types as
/// needed, though this should not be needed for RISC targets.
class Operand<ValueType ty> {
- int NumMIOperands = 1;
ValueType Type = ty;
string PrintMethod = "printOperand";
+ int NumMIOperands = 1;
+ dag MIOperandInfo = (ops);
}
def i1imm : Operand<i1>;
// which are global to the the target machine.
//
class InstrInfo {
- Instruction PHIInst;
-
// If the target wants to associate some target-specific information with each
// instruction, it should provide these two lists to indicate how to assemble
// the target specific information into the 32 bits available.
bit isLittleEndianEncoding = 0;
}
+// Standard Instructions.
+def PHI : Instruction {
+ let OperandList = (ops variable_ops);
+ let AsmString = "PHINODE";
+ let Namespace = "TargetInstrInfo";
+}
+def INLINEASM : Instruction {
+ let OperandList = (ops variable_ops);
+ let AsmString = "";
+ let Namespace = "TargetInstrInfo";
+}
+
//===----------------------------------------------------------------------===//
// AsmWriter - This class can be implemented by targets that need to customize
// the format of the .s file writer.
// Target - This class contains the "global" target information
//
class Target {
- // CalleeSavedRegisters - As you might guess, this is a list of the callee
- // saved registers for a target.
- list<Register> CalleeSavedRegisters = [];
-
- // PointerType - Specify the value type to be used to represent pointers in
- // this target. Typically this is an i32 or i64 type.
- ValueType PointerType;
-
// InstructionSet - Instruction set description for this target.
InstrInfo InstructionSet;
list<AsmWriter> AssemblyWriters = [DefaultAsmWriter];
}
-
//===----------------------------------------------------------------------===//
-// DAG node definitions used by the instruction selector.
-//
-// NOTE: all of this is a work-in-progress and should be ignored for now.
+// SubtargetFeature - A characteristic of the chip set.
//
-/*
-class Expander<dag pattern, list<dag> result> {
- dag Pattern = pattern;
- list<dag> Result = result;
-}
-
-class DagNodeValType;
-def DNVT_any : DagNodeValType; // No constraint on tree node
-def DNVT_void : DagNodeValType; // Tree node always returns void
-def DNVT_val : DagNodeValType; // A non-void type
-def DNVT_arg0 : DagNodeValType; // Tree node returns same type as Arg0
-def DNVT_arg1 : DagNodeValType; // Tree node returns same type as Arg1
-def DNVT_ptr : DagNodeValType; // The target pointer type
-def DNVT_i8 : DagNodeValType; // Always have an i8 value
-
-class DagNode<DagNodeValType ret, list<DagNodeValType> args> {
- DagNodeValType RetType = ret;
- list<DagNodeValType> ArgTypes = args;
- string EnumName = ?;
-}
-
-// BuiltinDagNodes are built into the instruction selector and correspond to
-// enum values.
-class BuiltinDagNode<DagNodeValType Ret, list<DagNodeValType> Args,
- string Ename> : DagNode<Ret, Args> {
- let EnumName = Ename;
+class SubtargetFeature<string n, string a, string v, string d> {
+ // Name - Feature name. Used by command line (-mattr=) to determine the
+ // appropriate target chip.
+ //
+ string Name = n;
+
+ // Attribute - Attribute to be set by feature.
+ //
+ string Attribute = a;
+
+ // Value - Value the attribute to be set to by feature.
+ //
+ string Value = v;
+
+ // Desc - Feature description. Used by command line (-mattr=) to display help
+ // information.
+ //
+ string Desc = d;
}
-// Magic nodes...
-def Void : RegisterClass<isVoid,0,[]> { let isDummyClass = 1; }
-def set : DagNode<DNVT_void, [DNVT_val, DNVT_arg0]>;
-def chain : BuiltinDagNode<DNVT_void, [DNVT_void, DNVT_void], "ChainNode">;
-def blockchain : BuiltinDagNode<DNVT_void, [DNVT_void, DNVT_void],
- "BlockChainNode">;
-def ChainExpander : Expander<(chain Void, Void), []>;
-def BlockChainExpander : Expander<(blockchain Void, Void), []>;
-
-
-// Terminals...
-def imm : BuiltinDagNode<DNVT_val, [], "Constant">;
-def frameidx : BuiltinDagNode<DNVT_ptr, [], "FrameIndex">;
-def basicblock : BuiltinDagNode<DNVT_ptr, [], "BasicBlock">;
-
-// Arithmetic...
-def plus : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "Plus">;
-def minus : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "Minus">;
-def times : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "Times">;
-def sdiv : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "SDiv">;
-def udiv : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "UDiv">;
-def srem : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "SRem">;
-def urem : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "URem">;
-def and : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "And">;
-def or : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "Or">;
-def xor : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "Xor">;
-
-// Comparisons...
-def seteq : BuiltinDagNode<DNVT_i8 , [DNVT_arg1, DNVT_arg0], "SetEQ">;
-def setne : BuiltinDagNode<DNVT_i8 , [DNVT_arg1, DNVT_arg0], "SetNE">;
-def setlt : BuiltinDagNode<DNVT_i8 , [DNVT_arg1, DNVT_arg0], "SetLT">;
-def setle : BuiltinDagNode<DNVT_i8 , [DNVT_arg1, DNVT_arg0], "SetLE">;
-def setgt : BuiltinDagNode<DNVT_i8 , [DNVT_arg1, DNVT_arg0], "SetGT">;
-def setge : BuiltinDagNode<DNVT_i8 , [DNVT_arg1, DNVT_arg0], "SetGE">;
-
-def load : BuiltinDagNode<DNVT_val, [DNVT_ptr], "Load">;
-//def store : BuiltinDagNode<DNVT_Void, [DNVT_ptr, DNVT_val]>;
-
-// Other...
-def ret : BuiltinDagNode<DNVT_void, [DNVT_val], "Ret">;
-def retvoid : BuiltinDagNode<DNVT_void, [], "RetVoid">;
-def br : BuiltinDagNode<DNVT_void, [DNVT_ptr], "Br">;
-def brcond : BuiltinDagNode<DNVT_void, [DNVT_i8, DNVT_ptr, DNVT_ptr],
- "BrCond">;
-
-def unspec1 : BuiltinDagNode<DNVT_any , [DNVT_val], "Unspec1">;
-def unspec2 : BuiltinDagNode<DNVT_any , [DNVT_val, DNVT_val], "Unspec2">;
-
//===----------------------------------------------------------------------===//
-// DAG nonterminals definitions used by the instruction selector...
+// Processor chip sets - These values represent each of the chip sets supported
+// by the scheduler. Each Processor definition requires corresponding
+// instruction itineraries.
//
-class Nonterminal<dag pattern> {
- dag Pattern = pattern;
- bit BuiltIn = 0;
+class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
+ // Name - Chip set name. Used by command line (-mcpu=) to determine the
+ // appropriate target chip.
+ //
+ string Name = n;
+
+ // ProcItin - The scheduling information for the target processor.
+ //
+ ProcessorItineraries ProcItin = pi;
+
+ // Features - list of
+ list<SubtargetFeature> Features = f;
}
-*/
+//===----------------------------------------------------------------------===//
+// Pull in the common support for DAG isel generation
+//
+include "TargetSelectionDAG.td"
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