Let X86CompilationCallback pass previous frame and return address to X86CompilationCa...

[oota-llvm.git] / lib / Target / Target.td

diff --git a/lib/Target/Target.td b/lib/Target/Target.td
index 663dfce91e49ba5cfd37fb15e88e2eb9271b6b7f..3e7665fd2e981f8fae29cf6a0130a6be93cf17c3 100644 (file)
--- a/lib/Target/Target.td
+++ b/lib/Target/Target.td
@@ -70,8 +70,11 @@ class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
                     list<Register> regList> {
   string Namespace = namespace;
 
-  // RegType - Specify the ValueType of the registers in this register class.
-  // Note that all registers in a register class must have the same ValueType.
+  // RegType - Specify the list ValueType of the registers in this register
+  // class.  Note that all registers in a register class must have the same
+  // ValueTypes.  This is a list because some targets permit storing different 
+  // types in same register, for example vector values with 128-bit total size,
+  // but different count/size of items, like SSE on x86.
   //
   list<ValueType> RegTypes = regTypes;
 
@@ -115,7 +118,7 @@ class DwarfRegNum<int N> {
 //===----------------------------------------------------------------------===//
 // Pull in the common support for scheduling
 //
-include "../TargetSchedule.td"
+include "TargetSchedule.td"
 
 class Predicate; // Forward def
 
@@ -186,6 +189,12 @@ def ops;
 /// of operands.
 def variable_ops;
 
+/// ptr_rc definition - Mark this operand as being a pointer value whose
+/// register class is resolved dynamically via a callback to TargetInstrInfo.
+/// FIXME: We should probably change this to a class which contain a list of
+/// flags. But currently we have but one flag.
+def ptr_rc;
+
 /// Operand Types - These provide the built-in operand types that may be used
 /// by a target.  Targets can optionally provide their own operand types as
 /// needed, though this should not be needed for RISC targets.
@@ -224,10 +233,12 @@ class InstrInfo {
 def PHI : Instruction {
   let OperandList = (ops variable_ops);
   let AsmString = "PHINODE";
+  let Namespace = "TargetInstrInfo";
 }
 def INLINEASM : Instruction {
   let OperandList = (ops variable_ops);
   let AsmString = "";
+  let Namespace = "TargetInstrInfo";
 }
 
 //===----------------------------------------------------------------------===//
@@ -262,14 +273,6 @@ def DefaultAsmWriter : AsmWriter;
 // Target - This class contains the "global" target information
 //
 class Target {
-  // CalleeSavedRegisters - As you might guess, this is a list of the callee
-  // saved registers for a target.
-  list<Register> CalleeSavedRegisters = [];
-  
-  // PointerType - Specify the value type to be used to represent pointers in
-  // this target.  Typically this is an i32 or i64 type.
-  ValueType PointerType;
-
   // InstructionSet - Instruction set description for this target.
   InstrInfo InstructionSet;
 
@@ -322,4 +325,4 @@ class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
 //===----------------------------------------------------------------------===//
 // Pull in the common support for DAG isel generation
 //
-include "../TargetSelectionDAG.td"
+include "TargetSelectionDAG.td"