//
//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-//
-// Value types - These values correspond to the register types defined in the
-// ValueTypes.h file. If you update anything here, you must update it there as
-// well!
-//
-class ValueType<int size, int value> {
- string Namespace = "MVT";
- int Size = size;
- int Value = value;
-}
-
-def OtherVT: ValueType<0 , 0>; // "Other" value
-def i1 : ValueType<1 , 1>; // One bit boolean value
-def i8 : ValueType<8 , 2>; // 8-bit integer value
-def i16 : ValueType<16 , 3>; // 16-bit integer value
-def i32 : ValueType<32 , 4>; // 32-bit integer value
-def i64 : ValueType<64 , 5>; // 64-bit integer value
-def i128 : ValueType<128, 6>; // 128-bit integer value
-def f32 : ValueType<32 , 7>; // 32-bit floating point value
-def f64 : ValueType<64 , 8>; // 64-bit floating point value
-def f80 : ValueType<80 , 9>; // 80-bit floating point value
-def f128 : ValueType<128, 10>; // 128-bit floating point value
-def FlagVT : ValueType<0 , 11>; // Condition code or machine flag
-def isVoid : ValueType<0 , 12>; // Produces no value
-def Vector : ValueType<0 , 13>; // Abstract vector value
-def v16i8 : ValueType<128, 14>; // 16 x i8 vector value
-def v8i16 : ValueType<128, 15>; // 8 x i16 vector value
-def v4i32 : ValueType<128, 16>; // 4 x i32 vector value
-def v2i64 : ValueType<128, 17>; // 2 x i64 vector value
-def v4f32 : ValueType<128, 18>; // 4 x f32 vector value
-def v2f64 : ValueType<128, 19>; // 2 x f64 vector value
+// Include all information about LLVM intrinsics.
+include "llvm/Intrinsics.td"
//===----------------------------------------------------------------------===//
// Register file description - These classes are used to fill in the target
// registers.
//
list<Register> Aliases = [];
+
+ // DwarfNumber - Number used internally by gcc/gdb to identify the register.
+ // These values can be determined by locating the <target>.h file in the
+ // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
+ // order of these names correspond to the enumeration used by gcc. A value of
+ // -1 indicates that the gcc number is undefined.
+ int DwarfNumber = -1;
}
// RegisterGroup - This can be used to define instances of Register which
list<Register> regList> {
string Namespace = namespace;
- // RegType - Specify the ValueType of the registers in this register class.
- // Note that all registers in a register class must have the same ValueType.
+ // RegType - Specify the list ValueType of the registers in this register
+ // class. Note that all registers in a register class must have the same
+ // ValueTypes. This is a list because some targets permit storing different
+ // types in same register, for example vector values with 128-bit total size,
+ // but different count/size of items, like SSE on x86.
//
list<ValueType> RegTypes = regTypes;
}
+//===----------------------------------------------------------------------===//
+// DwarfRegNum - This class provides a mapping of the llvm register enumeration
+// to the register numbering used by gcc and gdb. These values are used by a
+// debug information writer (ex. DwarfWriter) to describe where values may be
+// located during execution.
+class DwarfRegNum<int N> {
+ // DwarfNumber - Number used internally by gcc/gdb to identify the register.
+ // These values can be determined by locating the <target>.h file in the
+ // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
+ // order of these names correspond to the enumeration used by gcc. A value of
+ // -1 indicates that the gcc number is undefined.
+ int DwarfNumber = N;
+}
+
//===----------------------------------------------------------------------===//
// Pull in the common support for scheduling
//
-include "../TargetSchedule.td"
+include "TargetSchedule.td"
+class Predicate; // Forward def
//===----------------------------------------------------------------------===//
// Instruction set description - These classes correspond to the C++ classes in
list<Register> Uses = []; // Default to using no non-operand registers
list<Register> Defs = []; // Default to modifying no non-operand registers
+ // Predicates - List of predicates which will be turned into isel matching
+ // code.
+ list<Predicate> Predicates = [];
+
+ // Added complexity passed onto matching pattern.
+ int AddedComplexity = 0;
+
// These bits capture information about the high-level semantics of the
// instruction.
bit isReturn = 0; // Is this instruction a return instruction?
bit isTerminator = 0; // Is this part of the terminator for a basic block?
bit hasDelaySlot = 0; // Does this instruction have an delay slot?
bit usesCustomDAGSchedInserter = 0; // Pseudo instr needing special help.
+ bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
+ bit noResults = 0; // Does this instruction produce no results?
- InstrItinClass Itinerary; // Execution steps used for scheduling.
+ InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
+}
+
+/// Predicates - These are extra conditionals which are turned into instruction
+/// selector matching code. Currently each predicate is just a string.
+class Predicate<string cond> {
+ string CondString = cond;
}
+class Requires<list<Predicate> preds> {
+ list<Predicate> Predicates = preds;
+}
/// ops definition - This is just a simple marker used to identify the operands
/// list for an instruction. This should be used like this:
/// of operands.
def variable_ops;
+/// ptr_rc definition - Mark this operand as being a pointer value whose
+/// register class is resolved dynamically via a callback to TargetInstrInfo.
+/// FIXME: We should probably change this to a class which contain a list of
+/// flags. But currently we have but one flag.
+def ptr_rc;
+
/// Operand Types - These provide the built-in operand types that may be used
/// by a target. Targets can optionally provide their own operand types as
/// needed, though this should not be needed for RISC targets.
// which are global to the the target machine.
//
class InstrInfo {
- Instruction PHIInst;
-
// If the target wants to associate some target-specific information with each
// instruction, it should provide these two lists to indicate how to assemble
// the target specific information into the 32 bits available.
bit isLittleEndianEncoding = 0;
}
+// Standard Instructions.
+def PHI : Instruction {
+ let OperandList = (ops variable_ops);
+ let AsmString = "PHINODE";
+ let Namespace = "TargetInstrInfo";
+}
+def INLINEASM : Instruction {
+ let OperandList = (ops variable_ops);
+ let AsmString = "";
+ let Namespace = "TargetInstrInfo";
+}
+
//===----------------------------------------------------------------------===//
// AsmWriter - This class can be implemented by targets that need to customize
// the format of the .s file writer.
// Target - This class contains the "global" target information
//
class Target {
- // CalleeSavedRegisters - As you might guess, this is a list of the callee
- // saved registers for a target.
- list<Register> CalleeSavedRegisters = [];
-
- // PointerType - Specify the value type to be used to represent pointers in
- // this target. Typically this is an i32 or i64 type.
- ValueType PointerType;
-
// InstructionSet - Instruction set description for this target.
InstrInfo InstructionSet;
//===----------------------------------------------------------------------===//
// SubtargetFeature - A characteristic of the chip set.
//
-class SubtargetFeature<string n, string t, string a, string d> {
+class SubtargetFeature<string n, string a, string v, string d> {
// Name - Feature name. Used by command line (-mattr=) to determine the
// appropriate target chip.
//
string Name = n;
- // Type - Type of attribute to be set by feature.
- //
- string Type = t;
-
// Attribute - Attribute to be set by feature.
//
string Attribute = a;
+ // Value - Value the attribute to be set to by feature.
+ //
+ string Value = v;
+
// Desc - Feature description. Used by command line (-mattr=) to display help
// information.
//
//===----------------------------------------------------------------------===//
// Pull in the common support for DAG isel generation
//
-include "../TargetSelectionDAG.td"
+include "TargetSelectionDAG.td"
projects / oota-llvm.git / blobdiff