Fix loadv2i32 to be loadv4i32, though it isn't actually used anywhere yet.

[oota-llvm.git] / lib / Target / Target.td

diff --git a/lib/Target/Target.td b/lib/Target/Target.td
index 938e4cdc8fbf72092257d0921f195a0337bdad29..2258199ddf071be475f5677ccca1258613b54f56 100644 (file)
--- a/lib/Target/Target.td
+++ b/lib/Target/Target.td
@@ -109,6 +109,10 @@ class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
   // allocation used by the register allocator.
   //
   list<Register> MemberList = regList;
+  
+  // SubClassList - Specify which register classes correspond to subregisters
+  // of this class. The order should be by subregister set index.
+  list<RegisterClass> SubRegClassList = [];
 
   // MethodProtos/MethodBodies - These members can be used to insert arbitrary
   // code into a generated register class.   The normal usage of this is to 
@@ -182,11 +186,13 @@ class Instruction {
   bit isConvertibleToThreeAddress = 0;  // Can this 2-addr instruction promote?
   bit isCommutable = 0;     // Is this 3 operand instruction commutable?
   bit isTerminator = 0;     // Is this part of the terminator for a basic block?
-  bit isReMaterializable = 0; // Is this instruction re-materializable?
+  bit isPredicable = 0;     // Is this instruction predicable?
   bit hasDelaySlot = 0;     // Does this instruction have an delay slot?
   bit usesCustomDAGSchedInserter = 0; // Pseudo instr needing special help.
   bit hasCtrlDep   = 0;     // Does this instruction r/w ctrl-flow chains?
   bit noResults    = 0;     // Does this instruction produce no results?
+  bit clobbersPred = 0;     // Does it clobbers condition code / predicate?
+  bit isNotDuplicable = 0;  // Is it unsafe to duplicate this instruction?
   
   InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
 
@@ -254,7 +260,7 @@ def i64imm : Operand<i64>;
 /// instruction.  OpTypes specifies the MIOperandInfo for the operand, and
 /// AlwaysVal specifies the value of this predicate when set to "always
 /// execute".
-class PredicateOperand<dag OpTypes, dag AlwaysVal> : Operand<OtherVT> {
+class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal> : Operand<ty> {
   let MIOperandInfo = OpTypes;
   dag ExecuteAlways = AlwaysVal;
 }
@@ -338,7 +344,8 @@ class Target {
 //===----------------------------------------------------------------------===//
 // SubtargetFeature - A characteristic of the chip set.
 //
-class SubtargetFeature<string n, string a,  string v, string d> {
+class SubtargetFeature<string n, string a,  string v, string d,
+                       list<SubtargetFeature> i = []> {
   // Name - Feature name.  Used by command line (-mattr=) to determine the
   // appropriate target chip.
   //
@@ -356,6 +363,11 @@ class SubtargetFeature<string n, string a,  string v, string d> {
   // information.
   //
   string Desc = d;
+
+  // Implies - Features that this feature implies are present. If one of those
+  // features isn't set, then this one shouldn't be set either.
+  //
+  list<SubtargetFeature> Implies = i;
 }
 
 //===----------------------------------------------------------------------===//