// instructions.
struct Reference {
Reference()
- : Def(false), Use(false), IndirectDef(false), IndirectUse(false) {}
+ : Def(false), Use(false) {}
Reference &operator|=(const Reference &Other) {
Def |= Other.Def;
- IndirectDef |= Other.IndirectDef;
Use |= Other.Use;
- IndirectUse |= Other.IndirectUse;
return *this;
}
- operator bool() const { return Def || Use; }
+ explicit operator bool() const { return Def || Use; }
// True if the register is defined or used in some form, either directly or
// via a sub- or super-register.
bool Def;
bool Use;
-
- // True if the register is defined or used indirectly, by a sub- or
- // super-register.
- bool IndirectDef;
- bool IndirectUse;
};
class SystemZElimCompare : public MachineFunctionPass {
return false;
}
-// Return true if any CC result of MI would reflect the value of subreg
-// SubReg of Reg.
-static bool resultTests(MachineInstr *MI, unsigned Reg, unsigned SubReg) {
+// Return true if any CC result of MI would reflect the value of Reg.
+static bool resultTests(MachineInstr *MI, unsigned Reg) {
if (MI->getNumOperands() > 0 &&
MI->getOperand(0).isReg() &&
MI->getOperand(0).isDef() &&
- MI->getOperand(0).getReg() == Reg &&
- MI->getOperand(0).getSubReg() == SubReg)
+ MI->getOperand(0).getReg() == Reg)
return true;
switch (MI->getOpcode()) {
case SystemZ::LTEBR:
case SystemZ::LTDBR:
case SystemZ::LTXBR:
- if (MI->getOperand(1).getReg() == Reg &&
- MI->getOperand(1).getSubReg() == SubReg)
+ if (MI->getOperand(1).getReg() == Reg)
return true;
}
return false;
}
-// Describe the references to Reg in MI, including sub- and super-registers.
+// Describe the references to Reg or any of its aliases in MI.
Reference SystemZElimCompare::getRegReferences(MachineInstr *MI, unsigned Reg) {
Reference Ref;
for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) {
const MachineOperand &MO = MI->getOperand(I);
if (MO.isReg()) {
if (unsigned MOReg = MO.getReg()) {
- if (MOReg == Reg || TRI->regsOverlap(MOReg, Reg)) {
- if (MO.isUse()) {
+ if (TRI->regsOverlap(MOReg, Reg)) {
+ if (MO.isUse())
Ref.Use = true;
- Ref.IndirectUse |= (MOReg != Reg);
- }
- if (MO.isDef()) {
+ else if (MO.isDef())
Ref.Def = true;
- Ref.IndirectDef |= (MOReg != Reg);
- }
}
}
}
return Ref;
}
+// Return true if this is a load and test which can be optimized the
+// same way as compare instruction.
+static bool isLoadAndTestAsCmp(MachineInstr *MI) {
+ // If we during isel used a load-and-test as a compare with 0, the
+ // def operand is dead.
+ return ((MI->getOpcode() == SystemZ::LTEBR ||
+ MI->getOpcode() == SystemZ::LTDBR ||
+ MI->getOpcode() == SystemZ::LTXBR) &&
+ MI->getOperand(0).isDead());
+}
+
+// Return the source register of Compare, which is the unknown value
+// being tested.
+static unsigned getCompareSourceReg(MachineInstr *Compare) {
+ unsigned reg = 0;
+ if (Compare->isCompare())
+ reg = Compare->getOperand(0).getReg();
+ else if (isLoadAndTestAsCmp(Compare))
+ reg = Compare->getOperand(1).getReg();
+ assert (reg);
+
+ return reg;
+}
+
// Compare compares the result of MI against zero. If MI is an addition
// of -1 and if CCUsers is a single branch on nonzero, eliminate the addition
// and convert the branch to a BRCT(G). Return true on success.
// We already know that there are no references to the register between
// MI and Compare. Make sure that there are also no references between
// Compare and Branch.
- unsigned SrcReg = Compare->getOperand(0).getReg();
+ unsigned SrcReg = getCompareSourceReg(Compare);
MachineBasicBlock::iterator MBBI = Compare, MBBE = Branch;
for (++MBBI; MBBI != MBBE; ++MBBI)
if (getRegReferences(MBBI, SrcReg))
// The transformation is OK. Rebuild Branch as a BRCT(G).
MachineOperand Target(Branch->getOperand(2));
- Branch->RemoveOperand(2);
- Branch->RemoveOperand(1);
- Branch->RemoveOperand(0);
+ while (Branch->getNumOperands())
+ Branch->RemoveOperand(0);
Branch->setDesc(TII->get(BRCT));
MachineInstrBuilder(*Branch->getParent()->getParent(), Branch)
.addOperand(MI->getOperand(0))
.addOperand(MI->getOperand(1))
.addOperand(Target)
.addReg(SystemZ::CC, RegState::ImplicitDefine);
- MI->removeFromParent();
+ MI->eraseFromParent();
return true;
}
return true;
default:
+
+ if (isLoadAndTestAsCmp(Compare))
+ return true;
+
return (Compare->getNumExplicitOperands() == 2 &&
Compare->getOperand(1).isImm() &&
Compare->getOperand(1).getImm() == 0);
return false;
// Search back for CC results that are based on the first operand.
- unsigned SrcReg = Compare->getOperand(0).getReg();
- unsigned SrcSubReg = Compare->getOperand(0).getSubReg();
+ unsigned SrcReg = getCompareSourceReg(Compare);
MachineBasicBlock &MBB = *Compare->getParent();
MachineBasicBlock::iterator MBBI = Compare, MBBE = MBB.begin();
Reference CCRefs;
while (MBBI != MBBE) {
--MBBI;
MachineInstr *MI = MBBI;
- if (resultTests(MI, SrcReg, SrcSubReg)) {
+ if (resultTests(MI, SrcReg)) {
// Try to remove both MI and Compare by converting a branch to BRCT(G).
// We don't care in this case whether CC is modified between MI and
// Compare.
while (MBBI != MBB.begin()) {
MachineInstr *MI = --MBBI;
if (CompleteCCUsers &&
- MI->isCompare() &&
+ (MI->isCompare() || isLoadAndTestAsCmp(MI)) &&
(optimizeCompareZero(MI, CCUsers) ||
fuseCompareAndBranch(MI, CCUsers))) {
++MBBI;
- MI->removeFromParent();
+ MI->eraseFromParent();
Changed = true;
CCUsers.clear();
- CompleteCCUsers = true;
continue;
}
- Reference CCRefs(getRegReferences(MI, SystemZ::CC));
- if (CCRefs.Def) {
+ if (MI->definesRegister(SystemZ::CC)) {
CCUsers.clear();
- CompleteCCUsers = !CCRefs.IndirectDef;
+ CompleteCCUsers = true;
}
- if (CompleteCCUsers && CCRefs.Use)
+ if (MI->readsRegister(SystemZ::CC) && CompleteCCUsers)
CCUsers.push_back(MI);
}
return Changed;
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