-// $Id$
-//***************************************************************************
-// File:
-// Sparc.cpp
-//
-// Purpose:
-//
-// History:
-// 7/15/01 - Vikram Adve - Created
-//**************************************************************************/
+//===-- Sparc.cpp - General implementation file for the Sparc Target ------===//
+//
+// This file contains the code for the Sparc Target that does not fit in any of
+// the other files in this directory.
+//
+//===----------------------------------------------------------------------===//
-#include "llvm/Target/Sparc.h"
#include "SparcInternals.h"
-#include "llvm/Method.h"
-#include "llvm/CodeGen/InstrScheduling.h"
+#include "llvm/Target/TargetMachineImpls.h"
+#include "llvm/Function.h"
+#include "llvm/PassManager.h"
+#include "llvm/Transforms/Scalar.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/PreSelection.h"
+#include "llvm/CodeGen/StackSlots.h"
+#include "llvm/CodeGen/PeepholeOpts.h"
#include "llvm/CodeGen/InstrSelection.h"
-
-#include "llvm/Analysis/LiveVar/MethodLiveVarInfo.h"
-#include "llvm/CodeGen/PhyRegAlloc.h"
+#include "llvm/CodeGen/InstrScheduling.h"
+#include "llvm/CodeGen/RegisterAllocation.h"
+#include "llvm/CodeGen/MachineCodeForInstruction.h"
+#include "llvm/Reoptimizer/Mapping/MappingInfo.h"
+#include "llvm/Reoptimizer/Mapping/FInfo.h"
+#include "Support/CommandLine.h"
+using std::cerr;
// Build the MachineInstruction Description Array...
const MachineInstrDescriptor SparcMachineInstrDesc[] = {
#include "SparcInstr.def"
};
-//----------------------------------------------------------------------------
-// allocateSparcTargetMachine - Allocate and return a subclass of TargetMachine
-// that implements the Sparc backend. (the llvm/CodeGen/Sparc.h interface)
-//----------------------------------------------------------------------------
-//
+//---------------------------------------------------------------------------
+// Command line options to control choice of code generation passes.
+//---------------------------------------------------------------------------
-TargetMachine *allocateSparcTargetMachine() { return new UltraSparc(); }
+static cl::opt<bool> DisablePreSelect("nopreselect",
+ cl::desc("Disable preselection pass"));
+static cl::opt<bool> DisableSched("nosched",
+ cl::desc("Disable local scheduling pass"));
+
+static cl::opt<bool> DisablePeephole("nopeephole",
+ cl::desc("Disable peephole optimization pass"));
//----------------------------------------------------------------------------
-// Entry point for register allocation for a module
+// allocateSparcTargetMachine - Allocate and return a subclass of TargetMachine
+// that implements the Sparc backend. (the llvm/CodeGen/Sparc.h interface)
//----------------------------------------------------------------------------
-void AllocateRegisters(Method *M, TargetMachine &TM)
-{
-
- if ( (M)->isExternal() ) // don't process prototypes
- return;
-
- if( DEBUG_RA ) {
- cerr << endl << "******************** Method "<< (M)->getName();
- cerr << " ********************" <<endl;
- }
-
- MethodLiveVarInfo LVI(M ); // Analyze live varaibles
- LVI.analyze();
-
-
- PhyRegAlloc PRA(M, TM , &LVI); // allocate registers
- PRA.allocateRegisters();
-
-
- if( DEBUG_RA ) cerr << endl << "Register allocation complete!" << endl;
-
-}
+TargetMachine *allocateSparcTargetMachine() { return new UltraSparc(); }
//---------------------------------------------------------------------------
-// class UltraSparcSchedInfo
+// class UltraSparcFrameInfo
//
// Purpose:
-// Scheduling information for the UltraSPARC.
-// Primarily just initializes machine-dependent parameters in
-// class MachineSchedInfo.
+// Interface to stack frame layout info for the UltraSPARC.
+// Starting offsets for each area of the stack frame are aligned at
+// a multiple of getStackFrameSizeAlignment().
//---------------------------------------------------------------------------
-/*ctor*/
-UltraSparcSchedInfo::UltraSparcSchedInfo(const MachineInstrInfo* mii)
- : MachineSchedInfo((unsigned int) SPARC_NUM_SCHED_CLASSES,
- mii,
- SparcRUsageDesc,
- SparcInstrUsageDeltas,
- SparcInstrIssueDeltas,
- sizeof(SparcInstrUsageDeltas)/sizeof(InstrRUsageDelta),
- sizeof(SparcInstrIssueDeltas)/sizeof(InstrIssueDelta))
+int
+UltraSparcFrameInfo::getFirstAutomaticVarOffset(MachineFunction& ,
+ bool& pos) const
{
- maxNumIssueTotal = 4;
- longestIssueConflict = 0; // computed from issuesGaps[]
-
- branchMispredictPenalty = 4; // 4 for SPARC IIi
- branchTargetUnknownPenalty = 2; // 2 for SPARC IIi
- l1DCacheMissPenalty = 8; // 7 or 9 for SPARC IIi
- l1ICacheMissPenalty = 8; // ? for SPARC IIi
-
- inOrderLoads = true; // true for SPARC IIi
- inOrderIssue = true; // true for SPARC IIi
- inOrderExec = false; // false for most architectures
- inOrderRetire= true; // true for most architectures
-
- // must be called after above parameters are initialized.
- this->initializeResources();
+ pos = false; // static stack area grows downwards
+ return StaticAreaOffsetFromFP;
}
-void
-UltraSparcSchedInfo::initializeResources()
+int
+UltraSparcFrameInfo::getRegSpillAreaOffset(MachineFunction& mcInfo,
+ bool& pos) const
{
- // Compute MachineSchedInfo::instrRUsages and MachineSchedInfo::issueGaps
- MachineSchedInfo::initializeResources();
+ mcInfo.freezeAutomaticVarsArea(); // ensure no more auto vars are added
- // Machine-dependent fixups go here. None for now.
+ pos = false; // static stack area grows downwards
+ unsigned int autoVarsSize = mcInfo.getAutomaticVarsSize();
+ return StaticAreaOffsetFromFP - autoVarsSize;
}
+int
+UltraSparcFrameInfo::getTmpAreaOffset(MachineFunction& mcInfo,
+ bool& pos) const
+{
+ mcInfo.freezeAutomaticVarsArea(); // ensure no more auto vars are added
+ mcInfo.freezeSpillsArea(); // ensure no more spill slots are added
+
+ pos = false; // static stack area grows downwards
+ unsigned int autoVarsSize = mcInfo.getAutomaticVarsSize();
+ unsigned int spillAreaSize = mcInfo.getRegSpillsSize();
+ int offset = autoVarsSize + spillAreaSize;
+ return StaticAreaOffsetFromFP - offset;
+}
-
+int
+UltraSparcFrameInfo::getDynamicAreaOffset(MachineFunction& mcInfo,
+ bool& pos) const
+{
+ // Dynamic stack area grows downwards starting at top of opt-args area.
+ // The opt-args, required-args, and register-save areas are empty except
+ // during calls and traps, so they are shifted downwards on each
+ // dynamic-size alloca.
+ pos = false;
+ unsigned int optArgsSize = mcInfo.getMaxOptionalArgsSize();
+ if (int extra = optArgsSize % getStackFrameSizeAlignment())
+ optArgsSize += (getStackFrameSizeAlignment() - extra);
+ int offset = optArgsSize + FirstOptionalOutgoingArgOffsetFromSP;
+ assert((offset - OFFSET) % getStackFrameSizeAlignment() == 0);
+ return offset;
+}
//---------------------------------------------------------------------------
// class UltraSparcMachine
//---------------------------------------------------------------------------
UltraSparc::UltraSparc()
- : TargetMachine("UltraSparc-Native"),
- instrInfo(),
- schedInfo(&instrInfo),
- regInfo( this )
-{
- optSizeForSubWordData = 4;
- minMemOpWordSize = 8;
- maxAtomicMemOpWordSize = 8;
+ : TargetMachine("UltraSparc-Native", 4),
+ schedInfo(*this),
+ regInfo(*this),
+ frameInfo(*this),
+ cacheInfo(*this),
+ optInfo(*this) {
}
+// addPassesToEmitAssembly - This method controls the entire code generation
+// process for the ultra sparc.
+//
+bool UltraSparc::addPassesToEmitAssembly(PassManager &PM, std::ostream &Out)
+{
+ // Construct and initialize the MachineFunction object for this fn.
+ PM.add(createMachineCodeConstructionPass(*this));
+ //Insert empty stackslots in the stack frame of each function
+ //so %fp+offset-8 and %fp+offset-16 are empty slots now!
+ PM.add(createStackSlotsPass(*this));
-
-bool UltraSparc::compileMethod(Method *M) {
-
- if (SelectInstructionsForMethod(M, *this))
+ // Specialize LLVM code for this target machine and then
+ // run basic dataflow optimizations on LLVM code.
+ if (!DisablePreSelect)
{
- cerr << "Instruction selection failed for method " << M->getName()
- << "\n\n";
- return true;
+ PM.add(createPreSelectionPass(*this));
+ /* PM.add(createReassociatePass()); */
+ PM.add(createLICMPass());
+ PM.add(createGCSEPass());
}
-
- if (ScheduleInstructionsWithSSA(M, *this))
- {
- cerr << "Instruction scheduling before allocation failed for method "
- << M->getName() << "\n\n";
- return true;
- }
-
- AllocateRegisters(M, *this); // allocate registers
+ PM.add(createInstructionSelectionPass(*this));
- return false;
-}
+ if (!DisableSched)
+ PM.add(createInstructionSchedulingWithSSAPass(*this));
+ PM.add(getRegisterAllocator(*this));
+ PM.add(getPrologEpilogInsertionPass());
+ if (!DisablePeephole)
+ PM.add(createPeepholeOptsPass(*this));
+
+ PM.add(MappingInfoForFunction(Out));
+
+ // Output assembly language to the .s file. Assembly emission is split into
+ // two parts: Function output and Global value output. This is because
+ // function output is pipelined with all of the rest of code generation stuff,
+ // allowing machine code representations for functions to be free'd after the
+ // function has been emitted.
+ //
+ PM.add(getFunctionAsmPrinterPass(Out));
+ PM.add(createMachineCodeDestructionPass()); // Free stuff no longer needed
+
+ // Emit Module level assembly after all of the functions have been processed.
+ PM.add(getModuleAsmPrinterPass(Out));
+
+ // Emit bytecode to the assembly file into its special section next
+ PM.add(getEmitBytecodeToAsmPass(Out));
+ PM.add(getFunctionInfo(Out));
+ return false;
+}
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