#include "SparcInternals.h"
#include "SparcRegClassInfo.h"
-#include "llvm/Target/Sparc.h"
-#include "llvm/CodeGen/MachineCodeForMethod.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineFunctionInfo.h"
#include "llvm/CodeGen/PhyRegAlloc.h"
#include "llvm/CodeGen/InstrSelection.h"
-#include "llvm/CodeGen/InstrSelectionSupport.h"
-#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineCodeForInstruction.h"
#include "llvm/CodeGen/MachineInstrAnnot.h"
-#include "llvm/CodeGen/RegAllocCommon.h"
-#include "llvm/Analysis/LiveVar/FunctionLiveVarInfo.h"
+#include "llvm/CodeGen/FunctionLiveVarInfo.h" // FIXME: Remove
+#include "../../CodeGen/RegAlloc/RegAllocCommon.h" // FIXME!
#include "llvm/iTerminators.h"
#include "llvm/iOther.h"
#include "llvm/Function.h"
#include "llvm/DerivedTypes.h"
-#include <iostream>
-#include <values.h>
-using std::cerr;
-using std::vector;
+
+enum {
+ BadRegClass = ~0
+};
UltraSparcRegInfo::UltraSparcRegInfo(const UltraSparc &tgt)
- : MachineRegInfo(tgt), UltraSparcInfo(&tgt), NumOfIntArgRegs(6),
- NumOfFloatArgRegs(32), InvalidRegNum(1000) {
-
+ : TargetRegInfo(tgt), NumOfIntArgRegs(6), NumOfFloatArgRegs(32)
+{
MachineRegClassArr.push_back(new SparcIntRegClass(IntRegClassID));
MachineRegClassArr.push_back(new SparcFloatRegClass(FloatRegClassID));
MachineRegClassArr.push_back(new SparcIntCCRegClass(IntCCRegClassID));
MachineRegClassArr.push_back(new SparcFloatCCRegClass(FloatCCRegClassID));
+ MachineRegClassArr.push_back(new SparcSpecialRegClass(SpecialRegClassID));
assert(SparcFloatRegClass::StartOfNonVolatileRegs == 32 &&
"32 Float regs are used for float arg passing");
"o6"
};
-const char * const SparcIntRegClass::getRegName(unsigned reg) {
+const char * const SparcIntRegClass::getRegName(unsigned reg) const {
assert(reg < NumOfAllRegs);
return IntRegNames[reg];
}
"f60", "f61", "f62", "f63"
};
-const char * const SparcFloatRegClass::getRegName(unsigned reg) {
+const char * const SparcFloatRegClass::getRegName(unsigned reg) const {
assert (reg < NumOfAllRegs);
return FloatRegNames[reg];
}
"xcc", "ccr"
};
-const char * const SparcIntCCRegClass::getRegName(unsigned reg) {
+const char * const SparcIntCCRegClass::getRegName(unsigned reg) const {
assert(reg < 2);
return IntCCRegNames[reg];
}
"fcc0", "fcc1", "fcc2", "fcc3"
};
-const char * const SparcFloatCCRegClass::getRegName(unsigned reg) {
- assert (reg < 4);
+const char * const SparcFloatCCRegClass::getRegName(unsigned reg) const {
+ assert (reg < 5);
return FloatCCRegNames[reg];
}
-// given the unified register number, this gives the name
-// for generating assembly code or debugging.
-//
-const char * const UltraSparcRegInfo::getUnifiedRegName(int reg) const {
- if( reg < 32 )
- return SparcIntRegClass::getRegName(reg);
- else if ( reg < (64 + 32) )
- return SparcFloatRegClass::getRegName( reg - 32);
- else if( reg < (64+32+4) )
- return SparcFloatCCRegClass::getRegName( reg -32 - 64);
- else if( reg < (64+32+4+2) ) // two names: %xcc and %ccr
- return SparcIntCCRegClass::getRegName( reg -32 - 64 - 4);
- else if (reg== InvalidRegNum) //****** TODO: Remove */
- return "<*NoReg*>";
- else
- assert(0 && "Invalid register number");
- return "";
+static const char * const SpecialRegNames[] = {
+ "fsr"
+};
+
+const char * const SparcSpecialRegClass::getRegName(unsigned reg) const {
+ assert (reg < 1);
+ return SpecialRegNames[reg];
}
// Get unified reg number for frame pointer
}
-// Get the register number for the specified integer arg#,
-// assuming there are argNum total args, intArgNum int args,
-// and fpArgNum FP args preceding (and not including) this one.
-// Use INT regs for FP args if this is a varargs call.
+// Get the register number for the specified argument #argNo,
//
// Return value:
-// InvalidRegNum, if there is no int register available for the arg.
-// regNum, otherwise (this is NOT the unified reg. num).
+// getInvalidRegNum(), if there is no int register available for the arg.
+// regNum, otherwise (this is NOT the unified reg. num).
+// regClassId is set to the register class ID.
//
-inline int
+int
UltraSparcRegInfo::regNumForIntArg(bool inCallee, bool isVarArgsCall,
- unsigned argNo,
- unsigned intArgNo, unsigned fpArgNo,
- unsigned& regClassId) const
+ unsigned argNo, unsigned& regClassId) const
{
regClassId = IntRegClassID;
if (argNo >= NumOfIntArgRegs)
- return InvalidRegNum;
+ return getInvalidRegNum();
else
return argNo + (inCallee? SparcIntRegClass::i0 : SparcIntRegClass::o0);
}
-// Get the register number for the specified FP arg#,
-// assuming there are argNum total args, intArgNum int args,
-// and fpArgNum FP args preceding (and not including) this one.
+// Get the register number for the specified FP argument #argNo,
// Use INT regs for FP args if this is a varargs call.
//
// Return value:
-// InvalidRegNum, if there is no int register available for the arg.
-// regNum, otherwise (this is NOT the unified reg. num).
+// getInvalidRegNum(), if there is no int register available for the arg.
+// regNum, otherwise (this is NOT the unified reg. num).
+// regClassId is set to the register class ID.
//
-inline int
+int
UltraSparcRegInfo::regNumForFPArg(unsigned regType,
bool inCallee, bool isVarArgsCall,
- unsigned argNo,
- unsigned intArgNo, unsigned fpArgNo,
- unsigned& regClassId) const
+ unsigned argNo, unsigned& regClassId) const
{
if (isVarArgsCall)
- return regNumForIntArg(inCallee, isVarArgsCall, argNo, intArgNo, fpArgNo,
- regClassId);
+ return regNumForIntArg(inCallee, isVarArgsCall, argNo, regClassId);
else
{
regClassId = FloatRegClassID;
if (regType == FPSingleRegType)
return (argNo*2+1 >= NumOfFloatArgRegs)?
- InvalidRegNum : SparcFloatRegClass::f0 + (argNo * 2 + 1);
+ getInvalidRegNum() : SparcFloatRegClass::f0 + (argNo * 2 + 1);
else if (regType == FPDoubleRegType)
return (argNo*2 >= NumOfFloatArgRegs)?
- InvalidRegNum : SparcFloatRegClass::f0 + (argNo * 2);
+ getInvalidRegNum() : SparcFloatRegClass::f0 + (argNo * 2);
else
assert(0 && "Illegal FP register type");
return 0;
// The following 4 methods are used to find the RegType (SparcInternals.h)
// of a LiveRange, a Value, and for a given register unified reg number.
//
-int UltraSparcRegInfo::getRegType(unsigned regClassID,
- const Type* type) const {
+int UltraSparcRegInfo::getRegTypeForClassAndType(unsigned regClassID,
+ const Type* type) const
+{
switch (regClassID) {
- case IntRegClassID: return IntRegType;
- case FloatRegClassID: {
- if (type == Type::FloatTy)
- return FPSingleRegType;
- else if (type == Type::DoubleTy)
- return FPDoubleRegType;
- assert(0 && "Unknown type in FloatRegClass");
- }
- case IntCCRegClassID: return IntCCRegType;
- case FloatCCRegClassID: return FloatCCRegType;
+ case IntRegClassID: return IntRegType;
+ case FloatRegClassID:
+ if (type == Type::FloatTy) return FPSingleRegType;
+ else if (type == Type::DoubleTy) return FPDoubleRegType;
+ assert(0 && "Unknown type in FloatRegClass"); return 0;
+ case IntCCRegClassID: return IntCCRegType;
+ case FloatCCRegClassID: return FloatCCRegType;
+ case SpecialRegClassID: return SpecialRegType;
default: assert( 0 && "Unknown reg class ID"); return 0;
}
}
-int UltraSparcRegInfo::getRegType(const LiveRange *LR) const {
- return getRegType(LR->getRegClass()->getID(), LR->getType());
+int UltraSparcRegInfo::getRegType(const Type* type) const
+{
+ return getRegTypeForClassAndType(getRegClassIDOfType(type), type);
}
-int UltraSparcRegInfo::getRegType(const Value *Val) const {
- return getRegType(getRegClassIDOfValue(Val), Val->getType());
+int UltraSparcRegInfo::getRegType(const LiveRange *LR) const
+{
+ return getRegTypeForClassAndType(LR->getRegClassID(), LR->getType());
}
-int UltraSparcRegInfo::getRegType(int unifiedRegNum) const {
+int UltraSparcRegInfo::getRegType(int unifiedRegNum) const
+{
if (unifiedRegNum < 32)
return IntRegType;
else if (unifiedRegNum < (32 + 32))
return 0;
}
- if(isCCReg)
- return res + 2; // corresponidng condition code regiser
+ if (isCCReg)
+ return res + 2; // corresponding condition code register
else
return res;
}
-// To find the register class to which a specified register belongs
-//
-unsigned UltraSparcRegInfo::getRegClassIDOfReg(int unifiedRegNum) const {
- unsigned classId = 0;
- (void) getClassRegNum(unifiedRegNum, classId);
- return classId;
-}
-
unsigned UltraSparcRegInfo::getRegClassIDOfRegType(int regType) const {
switch(regType) {
case IntRegType: return IntRegClassID;
LiveRange *RetAddrLR = LRI.getLiveRangeForValue(RetAddrVal);
assert(RetAddrLR && "INTERNAL ERROR: No LR for return address of call!");
- unsigned RegClassID = RetAddrLR->getRegClass()->getID();
+ unsigned RegClassID = RetAddrLR->getRegClassID();
RetAddrLR->setColor(getUnifiedRegNum(IntRegClassID, SparcIntRegClass::o7));
}
assert(LR && "No live range found for method arg");
unsigned regType = getRegType(LR);
- unsigned regClassIDOfArgReg = MAXINT; // reg class of chosen reg (unused)
+ unsigned regClassIDOfArgReg = BadRegClass; // reg class of chosen reg (unused)
int regNum = (regType == IntRegType)
? regNumForIntArg(/*inCallee*/ true, isVarArgs,
- argNo, intArgNo++, fpArgNo, regClassIDOfArgReg)
+ argNo, regClassIDOfArgReg)
: regNumForFPArg(regType, /*inCallee*/ true, isVarArgs,
- argNo, intArgNo, fpArgNo++, regClassIDOfArgReg);
+ argNo, regClassIDOfArgReg);
- if(regNum != InvalidRegNum)
+ if(regNum != getInvalidRegNum())
LR->setSuggestedColor(regNum);
}
}
LiveRange *LR = LRI.getLiveRangeForValue(I);
assert( LR && "No live range found for method arg");
- unsigned regType = getRegType( LR );
- unsigned RegClassID = (LR->getRegClass())->getID();
+ unsigned regType = getRegType(LR);
+ unsigned RegClassID = LR->getRegClassID();
// Find whether this argument is coming in a register (if not, on stack)
// Also find the correct register the argument must use (UniArgReg)
//
bool isArgInReg = false;
- unsigned UniArgReg = InvalidRegNum; // reg that LR MUST be colored with
- unsigned regClassIDOfArgReg = MAXINT; // reg class of chosen reg
+ unsigned UniArgReg = getInvalidRegNum(); // reg that LR MUST be colored with
+ unsigned regClassIDOfArgReg = BadRegClass; // reg class of chosen reg
int regNum = (regType == IntRegType)
? regNumForIntArg(/*inCallee*/ true, isVarArgs,
- argNo, intArgNo++, fpArgNo, regClassIDOfArgReg)
+ argNo, regClassIDOfArgReg)
: regNumForFPArg(regType, /*inCallee*/ true, isVarArgs,
- argNo, intArgNo, fpArgNo++, regClassIDOfArgReg);
+ argNo, regClassIDOfArgReg);
- if(regNum != InvalidRegNum) {
+ if(regNum != getInvalidRegNum()) {
isArgInReg = true;
UniArgReg = getUnifiedRegNum( regClassIDOfArgReg, regNum);
}
regClassIDOfArgReg == IntRegClassID &&
"This should only be an Int register for an FP argument");
- int TmpOff = MachineCodeForMethod::get(Meth).pushTempValue(target,
+ int TmpOff = MachineFunction::get(Meth).getInfo()->pushTempValue(
getSpilledRegSize(regType));
cpReg2MemMI(FirstAI->InstrnsBefore,
UniArgReg, getFramePointer(), TmpOff, IntRegType);
// Now the arg is coming on stack. Since the LR recieved a register,
// we just have to load the arg on stack into that register
//
- const MachineFrameInfo& frameInfo = target.getFrameInfo();
+ const TargetFrameInfo& frameInfo = target.getFrameInfo();
int offsetFromFP =
- frameInfo.getIncomingArgOffset(MachineCodeForMethod::get(Meth),
+ frameInfo.getIncomingArgOffset(MachineFunction::get(Meth),
argNo);
-
+
+ // float arguments on stack are right justified so adjust the offset!
+ // int arguments are also right justified but they are always loaded as
+ // a full double-word so the offset does not need to be adjusted.
+ if (regType == FPSingleRegType) {
+ unsigned argSize = target.getTargetData().getTypeSize(LR->getType());
+ unsigned slotSize = frameInfo.getSizeOfEachArgOnStack();
+ assert(argSize <= slotSize && "Insufficient slot size!");
+ offsetFromFP += slotSize - argSize;
+ }
+
cpMem2RegMI(FirstAI->InstrnsBefore,
getFramePointer(), offsetFromFP, UniLRReg, regType);
}
// can simply change the stack position of the LR. We can do this,
// since this method is called before any other method that makes
// uses of the stack pos of the LR (e.g., updateMachineInstr)
-
- const MachineFrameInfo& frameInfo = target.getFrameInfo();
+ //
+ const TargetFrameInfo& frameInfo = target.getFrameInfo();
int offsetFromFP =
- frameInfo.getIncomingArgOffset(MachineCodeForMethod::get(Meth),
+ frameInfo.getIncomingArgOffset(MachineFunction::get(Meth),
argNo);
+
+ // FP arguments on stack are right justified so adjust offset!
+ // int arguments are also right justified but they are always loaded as
+ // a full double-word so the offset does not need to be adjusted.
+ if (regType == FPSingleRegType) {
+ unsigned argSize = target.getTargetData().getTypeSize(LR->getType());
+ unsigned slotSize = frameInfo.getSizeOfEachArgOnStack();
+ assert(argSize <= slotSize && "Insufficient slot size!");
+ offsetFromFP += slotSize - argSize;
+ }
LR->modifySpillOffFromFP( offsetFromFP );
}
//---------------------------------------------------------------------------
void UltraSparcRegInfo::suggestRegs4CallArgs(MachineInstr *CallMI,
LiveRangeInfo& LRI) const {
- assert ( (UltraSparcInfo->getInstrInfo()).isCall(CallMI->getOpCode()) );
+ assert ( (target.getInstrInfo()).isCall(CallMI->getOpCode()) );
CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
LiveRange *RetValLR = LRI.getLiveRangeForValue(RetVal);
assert(RetValLR && "No LR for return Value of call!");
- unsigned RegClassID = RetValLR->getRegClass()->getID();
+ unsigned RegClassID = RetValLR->getRegClassID();
// now suggest a register depending on the register class of ret arg
if( RegClassID == IntRegClassID )
// get the LR of call operand (parameter)
LiveRange *const LR = LRI.getLiveRangeForValue(CallArg);
- assert (LR && "Must have a LR for all arguments since "
- "all args (even consts) must be defined before");
+ if (!LR)
+ continue; // no live ranges for constants and labels
- unsigned regType = getRegType( LR );
- unsigned regClassIDOfArgReg = MAXINT; // reg class of chosen reg (unused)
+ unsigned regType = getRegType(LR);
+ unsigned regClassIDOfArgReg = BadRegClass; // chosen reg class (unused)
// Choose a register for this arg depending on whether it is
// an INT or FP value. Here we ignore whether or not it is a
// to an integer Value and handled under (argCopy != NULL) below.
int regNum = (regType == IntRegType)
? regNumForIntArg(/*inCallee*/ false, /*isVarArgs*/ false,
- argNo, intArgNo++, fpArgNo, regClassIDOfArgReg)
+ argNo, regClassIDOfArgReg)
: regNumForFPArg(regType, /*inCallee*/ false, /*isVarArgs*/ false,
- argNo, intArgNo, fpArgNo++, regClassIDOfArgReg);
+ argNo, regClassIDOfArgReg);
// If a register could be allocated, use it.
// If not, do NOTHING as this will be colored as a normal value.
- if(regNum != InvalidRegNum)
+ if(regNum != getInvalidRegNum())
LR->setSuggestedColor(regNum);
+#ifdef CANNOT_PRECOPY_CALLARGS
// Repeat for the second copy of the argument, which would be
// an FP argument being passed to a function with no prototype
const Value *argCopy = argDesc->getArgInfo(i).getArgCopy();
assert(regType != IntRegType && argCopy->getType()->isInteger()
&& "Must be passing copy of FP argument in int register");
int copyRegNum = regNumForIntArg(/*inCallee*/false, /*isVarArgs*/false,
- argNo, intArgNo, fpArgNo-1,
- regClassIDOfArgReg);
- assert(copyRegNum != InvalidRegNum);
+ argNo, regClassIDOfArgReg);
+ assert(copyRegNum != getInvalidRegNum());
LiveRange *const copyLR = LRI.getLiveRangeForValue(argCopy);
copyLR->setSuggestedColor(copyRegNum);
}
+#endif
} // for all call arguments
AddedInstrns *CallAI,
PhyRegAlloc &PRA, LiveRange* LR,
unsigned regType, unsigned RegClassID,
- int UniArgRegOrNone, unsigned int argNo,
- std::vector<MachineInstr *>& AddedInstrnsBefore)
+ int UniArgRegOrNone, unsigned argNo,
+ std::vector<MachineInstr*> &AddedInstrnsBefore)
const
{
+ assert(0 && "Should never get here because we are now using precopying!");
+
MachineInstr *AdMI;
bool isArgInReg = false;
- unsigned UniArgReg = MAXINT; // unused unless initialized below
- if (UniArgRegOrNone != InvalidRegNum)
+ unsigned UniArgReg = BadRegClass; // unused unless initialized below
+ if (UniArgRegOrNone != getInvalidRegNum())
{
isArgInReg = true;
UniArgReg = (unsigned) UniArgRegOrNone;
- CallMI->getRegsUsed().insert(UniArgReg); // mark the reg as used
}
if (LR->hasColor()) {
}
else {
// Copy UniLRReg to the stack to pass the arg on stack.
- const MachineFrameInfo& frameInfo = target.getFrameInfo();
- int argOffset = frameInfo.getOutgoingArgOffset(PRA.mcInfo, argNo);
+ const TargetFrameInfo& frameInfo = target.getFrameInfo();
+ int argOffset = frameInfo.getOutgoingArgOffset(PRA.MF, argNo);
cpReg2MemMI(CallAI->InstrnsBefore,
UniLRReg, getStackPointer(), argOffset, regType);
}
// Use TReg to load and store the value.
// Use TmpOff to save TReg, since that may have a live value.
//
- int TReg = PRA.getUniRegNotUsedByThisInst( LR->getRegClass(), CallMI );
- int TmpOff = PRA.mcInfo.pushTempValue(target,
- getSpilledRegSize(getRegType(LR)));
- const MachineFrameInfo& frameInfo = target.getFrameInfo();
- int argOffset = frameInfo.getOutgoingArgOffset(PRA.mcInfo, argNo);
+ int TReg = PRA.getUniRegNotUsedByThisInst(LR->getRegClass(), CallMI);
+ int TmpOff = PRA.MF.getInfo()->
+ pushTempValue(getSpilledRegSize(getRegType(LR)));
+ const TargetFrameInfo& frameInfo = target.getFrameInfo();
+ int argOffset = frameInfo.getOutgoingArgOffset(PRA.MF, argNo);
MachineInstr *Ad1, *Ad2, *Ad3, *Ad4;
PhyRegAlloc &PRA,
const BasicBlock *BB) const {
- assert ( (UltraSparcInfo->getInstrInfo()).isCall(CallMI->getOpCode()) );
+ assert ( (target.getInstrInfo()).isCall(CallMI->getOpCode()) );
CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
if (RetVal) {
LiveRange *RetValLR = LRI.getLiveRangeForValue( RetVal );
+ assert(RetValLR && "ERROR: No LR for non-void return value");
- if (!RetValLR) {
- cerr << "\nNo LR for:" << RAV(RetVal) << "\n";
- assert(RetValLR && "ERR:No LR for non-void return value");
- }
-
- unsigned RegClassID = (RetValLR->getRegClass())->getID();
- bool recvCorrectColor;
- unsigned CorrectCol; // correct color for ret value
- unsigned UniRetReg; // unified number for CorrectCol
+ // Mark the return value register as used by this instruction
+ unsigned RegClassID = RetValLR->getRegClassID();
+ unsigned CorrectCol = (RegClassID == IntRegClassID
+ ? (unsigned) SparcIntRegClass::o0
+ : (unsigned) SparcFloatRegClass::f0);
- if(RegClassID == IntRegClassID)
- CorrectCol = SparcIntRegClass::o0;
- else if(RegClassID == FloatRegClassID)
- CorrectCol = SparcFloatRegClass::f0;
- else {
- assert( 0 && "Unknown RegClass");
- return;
- }
+ CallMI->insertUsedReg(getUnifiedRegNum(RegClassID, CorrectCol));
- // convert to unified number
- UniRetReg = getUnifiedRegNum(RegClassID, CorrectCol);
+#ifdef CANNOT_PRECOPY_CALLARGS
+ // unified number for CorrectCol
+ unsigned UniRetReg = getUnifiedRegNum(RegClassID, CorrectCol);
+ recvCorrectColor;
- // Mark the register as used by this instruction
- CallMI->getRegsUsed().insert(UniRetReg);
-
// if the LR received the correct color, NOTHING to do
- recvCorrectColor = RetValLR->hasColor()? RetValLR->getColor() == CorrectCol
- : false;
+ bool recvCorrectColor = (RetValLR->hasColor()
+ ? RetValLR->getColor() == CorrectCol : false);
// if we didn't receive the correct color for some reason,
// put copy instruction
if( !recvCorrectColor ) {
- unsigned regType = getRegType( RetValLR );
+ unsigned regType = getRegType(RetValLR);
if( RetValLR->hasColor() ) {
cpReg2MemMI(CallAI->InstrnsAfter, UniRetReg,
getFramePointer(),RetValLR->getSpillOffFromFP(), regType);
}
-
} // the LR didn't receive the suggested color
+#endif
} // if there a return value
// Now color all args of the call instruction
//-------------------------------------------
- std::vector<MachineInstr *> AddedInstrnsBefore;
+ std::vector<MachineInstr*> AddedInstrnsBefore;
unsigned NumOfCallArgs = argDesc->getNumArgs();
for(unsigned argNo=0, i=0, intArgNo=0, fpArgNo=0;
i < NumOfCallArgs; ++i, ++argNo) {
-
- const Value *CallArg = argDesc->getArgInfo(i).getArgVal();
- // get the LR of call operand (parameter)
- LiveRange *const LR = LRI.getLiveRangeForValue(CallArg);
+ const Value *CallArg = argDesc->getArgInfo(i).getArgVal();
+ unsigned regType = getRegType(CallArg->getType());
- unsigned RegClassID = getRegClassIDOfValue( CallArg);
- unsigned regType = getRegType( RegClassID, CallArg->getType() );
-
// Find whether this argument is coming in a register (if not, on stack)
// Also find the correct register the argument must use (UniArgReg)
//
bool isArgInReg = false;
- unsigned UniArgReg = InvalidRegNum; // reg that LR MUST be colored with
- unsigned regClassIDOfArgReg = MAXINT; // reg class of chosen reg
+ int UniArgReg = getInvalidRegNum(); // reg that LR MUST be colored with
+ unsigned regClassIDOfArgReg = BadRegClass; // reg class of chosen reg
// Find the register that must be used for this arg, depending on
// whether it is an INT or FP value. Here we ignore whether or not it
// is a varargs calls, because FP arguments will be explicitly copied
// to an integer Value and handled under (argCopy != NULL) below.
+ //
int regNum = (regType == IntRegType)
? regNumForIntArg(/*inCallee*/ false, /*isVarArgs*/ false,
- argNo, intArgNo++, fpArgNo, regClassIDOfArgReg)
+ argNo, regClassIDOfArgReg)
: regNumForFPArg(regType, /*inCallee*/ false, /*isVarArgs*/ false,
- argNo, intArgNo, fpArgNo++, regClassIDOfArgReg);
+ argNo, regClassIDOfArgReg);
- if(regNum != InvalidRegNum) {
+ if (regNum != getInvalidRegNum()) {
isArgInReg = true;
- UniArgReg = getUnifiedRegNum( regClassIDOfArgReg, regNum);
- assert(regClassIDOfArgReg == RegClassID &&
- "Moving values between reg classes must happen during selection");
+ UniArgReg = getUnifiedRegNum(regClassIDOfArgReg, regNum);
+ CallMI->insertUsedReg(UniArgReg); // mark the reg as used
}
+
+#ifdef CANNOT_PRECOPY_CALLARGS
- // not possible to have a null LR since all args (even consts)
- // must be defined before
- if (!LR) {
- cerr << " ERROR: In call instr, no LR for arg: " << RAV(CallArg) <<"\n";
- assert(LR && "NO LR for call arg");
+ // Get the LR of call operand (parameter). There must be one because
+ // all args (even constants) must be defined before.
+ LiveRange *const LR = LRI.getLiveRangeForValue(CallArg);
+ assert(LR && "NO LR for call arg");
+
+ unsigned RegClassID = getRegClassIDOfType(CallArg->getType());
+
+ if (regNum != getInvalidRegNum()) {
+ assert(regClassIDOfArgReg == RegClassID &&
+ "Moving values between reg classes must happen during selection");
}
InitializeOutgoingArg(CallMI, CallAI, PRA, LR, regType, RegClassID,
UniArgReg, argNo, AddedInstrnsBefore);
+#endif
// Repeat for the second copy of the argument, which would be
// an FP argument being passed to a function with no prototype.
// It may either be passed as a copy in an integer register
// (in argCopy), or on the stack (useStackSlot).
- const Value *argCopy = argDesc->getArgInfo(i).getArgCopy();
- if (argCopy != NULL)
+ int argCopyReg = argDesc->getArgInfo(i).getArgCopy();
+ if (argCopyReg != TargetRegInfo::getInvalidRegNum())
{
+ CallMI->insertUsedReg(argCopyReg); // mark the reg as used
+
+#ifdef CANNOT_PRECOPY_CALLARGS
assert(regType != IntRegType && argCopy->getType()->isInteger()
&& "Must be passing copy of FP argument in int register");
- unsigned copyRegClassID = getRegClassIDOfValue(argCopy);
- unsigned copyRegType = getRegType(copyRegClassID, argCopy->getType());
+ unsigned copyRegClassID = getRegClassIDOfType(argCopy->getType());
+ unsigned copyRegType = getRegType(argCopy->getType());
int copyRegNum = regNumForIntArg(/*inCallee*/false, /*isVarArgs*/false,
- argNo, intArgNo, fpArgNo-1,
- regClassIDOfArgReg);
- assert(copyRegNum != InvalidRegNum);
+ argNo, regClassIDOfArgReg);
+ assert(copyRegNum != getInvalidRegNum());
assert(regClassIDOfArgReg == copyRegClassID &&
"Moving values between reg classes must happen during selection");
LRI.getLiveRangeForValue(argCopy), copyRegType,
copyRegClassID, copyRegNum, argNo,
AddedInstrnsBefore);
+#endif
}
- if (regNum != InvalidRegNum &&
+#ifdef CANNOT_PRECOPY_CALLARGS
+ if (regNum != getInvalidRegNum() &&
argDesc->getArgInfo(i).usesStackSlot())
{
// Pass the argument via the stack in addition to regNum
assert(regType != IntRegType && "Passing an integer arg. twice?");
assert(!argCopy && "Passing FP arg in FP reg, INT reg, and stack?");
InitializeOutgoingArg(CallMI, CallAI, PRA, LR, regType, RegClassID,
- InvalidRegNum, argNo, AddedInstrnsBefore);
+ getInvalidRegNum(), argNo, AddedInstrnsBefore);
}
+#endif
} // for each parameter in call instruction
// If we added any instruction before the call instruction, verify
// that they are in the proper order and if not, reorder them
//
- std::vector<MachineInstr *> ReorderedVec;
+ std::vector<MachineInstr*> ReorderedVec;
if (!AddedInstrnsBefore.empty()) {
if (DEBUG_RA) {
- cerr << "\nCalling reorder with instrns: \n";
+ std::cerr << "\nCalling reorder with instrns: \n";
for(unsigned i=0; i < AddedInstrnsBefore.size(); i++)
- cerr << *(AddedInstrnsBefore[i]);
+ std::cerr << *(AddedInstrnsBefore[i]);
}
OrderAddedInstrns(AddedInstrnsBefore, ReorderedVec, PRA);
&& "Dropped some instructions when reordering!");
if (DEBUG_RA) {
- cerr << "\nAfter reordering instrns: \n";
+ std::cerr << "\nAfter reordering instrns: \n";
for(unsigned i = 0; i < ReorderedVec.size(); i++)
- cerr << *ReorderedVec[i];
+ std::cerr << *ReorderedVec[i];
}
}
//
for(unsigned i=0; i < ReorderedVec.size(); i++)
CallAI->InstrnsBefore.push_back( ReorderedVec[i] );
+
+#ifndef NDEBUG
+ // Temporary sanity checking code to detect whether the same machine
+ // instruction is ever inserted twice before/after a call.
+ // I suspect this is happening but am not sure. --Vikram, 7/1/03.
+ //
+ std::set<const MachineInstr*> instrsSeen;
+ for (int i = 0, N = CallAI->InstrnsBefore.size(); i < N; ++i) {
+ assert(instrsSeen.find(CallAI->InstrnsBefore[i]) == instrsSeen.end() &&
+ "Duplicate machine instruction in InstrnsBefore!");
+ instrsSeen.insert(CallAI->InstrnsBefore[i]);
+ }
+ for (int i = 0, N = CallAI->InstrnsAfter.size(); i < N; ++i) {
+ assert(instrsSeen.find(CallAI->InstrnsAfter[i]) == instrsSeen.end() &&
+ "Duplicate machine instruction in InstrnsBefore/After!");
+ instrsSeen.insert(CallAI->InstrnsAfter[i]);
+ }
+#endif
}
//---------------------------------------------------------------------------
-// This method is called for an LLVM return instruction to identify which
+// this method is called for an LLVM return instruction to identify which
// values will be returned from this method and to suggest colors.
//---------------------------------------------------------------------------
void UltraSparcRegInfo::suggestReg4RetValue(MachineInstr *RetMI,
LiveRangeInfo &LRI) const {
- assert( (UltraSparcInfo->getInstrInfo()).isReturn( RetMI->getOpCode() ) );
+ assert( (target.getInstrInfo()).isReturn( RetMI->getOpCode() ) );
suggestReg4RetAddr(RetMI, LRI);
- // if there is an implicit ref, that has to be the ret value
- if( RetMI->getNumImplicitRefs() > 0 ) {
-
- // The first implicit operand is the return value of a return instr
- const Value *RetVal = RetMI->getImplicitRef(0);
-
- LiveRange *const LR = LRI.getLiveRangeForValue( RetVal );
-
- if (!LR) {
- cerr << "\nNo LR for:" << RAV(RetVal) << "\n";
- assert(0 && "No LR for return value of non-void method");
- }
-
- unsigned RegClassID = (LR->getRegClass())->getID();
-
- if (RegClassID == IntRegClassID)
- LR->setSuggestedColor(SparcIntRegClass::i0);
- else if (RegClassID == FloatRegClassID)
- LR->setSuggestedColor(SparcFloatRegClass::f0);
- }
+ // To find the return value (if any), we can get the LLVM return instr.
+ // from the return address register, which is the first operand
+ Value* tmpI = RetMI->getOperand(0).getVRegValue();
+ ReturnInst* retI=cast<ReturnInst>(cast<TmpInstruction>(tmpI)->getOperand(0));
+ if (const Value *RetVal = retI->getReturnValue())
+ if (LiveRange *const LR = LRI.getLiveRangeForValue(RetVal))
+ LR->setSuggestedColor(LR->getRegClassID() == IntRegClassID
+ ? (unsigned) SparcIntRegClass::i0
+ : (unsigned) SparcFloatRegClass::f0);
}
LiveRangeInfo &LRI,
AddedInstrns *RetAI) const {
- assert((UltraSparcInfo->getInstrInfo()).isReturn( RetMI->getOpCode()));
+ assert((target.getInstrInfo()).isReturn( RetMI->getOpCode()));
- // if there is an implicit ref, that has to be the ret value
- if(RetMI->getNumImplicitRefs() > 0) {
+ // To find the return value (if any), we can get the LLVM return instr.
+ // from the return address register, which is the first operand
+ Value* tmpI = RetMI->getOperand(0).getVRegValue();
+ ReturnInst* retI=cast<ReturnInst>(cast<TmpInstruction>(tmpI)->getOperand(0));
+ if (const Value *RetVal = retI->getReturnValue()) {
- // The first implicit operand is the return value of a return instr
- const Value *RetVal = RetMI->getImplicitRef(0);
-
- LiveRange *LR = LRI.getLiveRangeForValue(RetVal);
-
- if (!LR) {
- cerr << "\nNo LR for:" << RAV(RetVal) << "\n";
- // assert( LR && "No LR for return value of non-void method");
- return;
- }
-
- unsigned RegClassID = getRegClassIDOfValue(RetVal);
- unsigned regType = getRegType( RetVal );
-
- unsigned CorrectCol;
- if(RegClassID == IntRegClassID)
- CorrectCol = SparcIntRegClass::i0;
- else if(RegClassID == FloatRegClassID)
- CorrectCol = SparcFloatRegClass::f0;
- else {
- assert (0 && "Unknown RegClass");
- return;
- }
+ unsigned RegClassID = getRegClassIDOfType(RetVal->getType());
+ unsigned regType = getRegType(RetVal->getType());
+ unsigned CorrectCol = (RegClassID == IntRegClassID
+ ? (unsigned) SparcIntRegClass::i0
+ : (unsigned) SparcFloatRegClass::f0);
// convert to unified number
unsigned UniRetReg = getUnifiedRegNum(RegClassID, CorrectCol);
// Mark the register as used by this instruction
- RetMI->getRegsUsed().insert(UniRetReg);
-
- // if the LR received the correct color, NOTHING to do
-
- if (LR->hasColor() && LR->getColor() == CorrectCol)
- return;
-
- if (LR->hasColor()) {
+ RetMI->insertUsedReg(UniRetReg);
- // We are here because the LR was allocted a regiter
+#ifdef CANNOT_PRECOPY_CALLARGS
+ LiveRange *LR = LRI.getLiveRangeForValue(RetVal);
+ assert(LR && "No LR for return value of non-void method?");
+
+ if (LR->hasColor()) {
+ // if the LR received the correct color, NOTHING to do
+ if (LR->getColor() == CorrectCol)
+ return;
+
+ // We are here because the LR was allocated a register
// It may be the suggested register or not
// copy the LR of retun value to i0 or f0
else { // if the LR is spilled
cpMem2RegMI(RetAI->InstrnsBefore, getFramePointer(),
LR->getSpillOffFromFP(), UniRetReg, regType);
- cerr << "\nCopied the return value from stack\n";
+ //std::cerr << "\nCopied the return value from stack\n";
}
+#endif
} // if there is a return value
//---------------------------------------------------------------------------
void
-UltraSparcRegInfo::cpReg2RegMI(vector<MachineInstr*>& mvec,
+UltraSparcRegInfo::cpReg2RegMI(std::vector<MachineInstr*>& mvec,
unsigned SrcReg,
unsigned DestReg,
int RegType) const {
- assert( ((int)SrcReg != InvalidRegNum) && ((int)DestReg != InvalidRegNum) &&
+ assert( ((int)SrcReg != getInvalidRegNum()) &&
+ ((int)DestReg != getInvalidRegNum()) &&
"Invalid Register");
MachineInstr * MI = NULL;
switch( RegType ) {
case IntCCRegType:
- if (getRegType(DestReg) == IntRegType)
- { // copy intCC reg to int reg
- // Use SrcReg+1 to get the name "%ccr" instead of "%xcc" for RDCCR
- MI = Create2OperandInstr_Reg(RDCCR, SrcReg+1, DestReg);
- }
- else
- { // copy int reg to intCC reg
- // Use DestReg+1 to get the name "%ccr" instead of "%xcc" for WRCCR
- assert(getRegType(SrcReg) == IntRegType
- && "Can only copy CC reg to/from integer reg");
- MI = Create2OperandInstr_Reg(WRCCR, SrcReg, DestReg+1);
- }
+ if (getRegType(DestReg) == IntRegType) {
+ // copy intCC reg to int reg
+ // Use SrcReg+1 to get the name "%ccr" instead of "%xcc" for RDCCR
+ MI = BuildMI(V9::RDCCR, 2).addMReg(SrcReg+1).addMReg(DestReg,MOTy::Def);
+ } else {
+ // copy int reg to intCC reg
+ // Use DestReg+1 to get the name "%ccr" instead of "%xcc" for WRCCR
+ assert(getRegType(SrcReg) == IntRegType
+ && "Can only copy CC reg to/from integer reg");
+ MI = BuildMI(V9::WRCCRr, 3).addMReg(SrcReg)
+ .addMReg(SparcIntRegClass::g0).addMReg(DestReg+1, MOTy::Def);
+ }
break;
case FloatCCRegType:
break;
case IntRegType:
- MI = Create3OperandInstr_Reg(ADD, SrcReg, getZeroRegNum(), DestReg);
+ MI = BuildMI(V9::ADDr, 3).addMReg(SrcReg).addMReg(getZeroRegNum())
+ .addMReg(DestReg, MOTy::Def);
break;
case FPSingleRegType:
- MI = Create2OperandInstr_Reg(FMOVS, SrcReg, DestReg);
+ MI = BuildMI(V9::FMOVS, 2).addMReg(SrcReg).addMReg(DestReg, MOTy::Def);
break;
case FPDoubleRegType:
- MI = Create2OperandInstr_Reg(FMOVD, SrcReg, DestReg);
+ MI = BuildMI(V9::FMOVD, 2).addMReg(SrcReg).addMReg(DestReg, MOTy::Def);
break;
default:
void
-UltraSparcRegInfo::cpReg2MemMI(vector<MachineInstr*>& mvec,
+UltraSparcRegInfo::cpReg2MemMI(std::vector<MachineInstr*>& mvec,
unsigned SrcReg,
unsigned DestPtrReg,
int Offset, int RegType,
int scratchReg) const {
MachineInstr * MI = NULL;
- switch( RegType ) {
+ switch (RegType) {
case IntRegType:
- MI = new MachineInstr(STX, 3);
- MI->SetMachineOperandReg(0, SrcReg, false);
- MI->SetMachineOperandReg(1, DestPtrReg, false);
- MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed,
- (int64_t) Offset);
- mvec.push_back(MI);
+ assert(target.getInstrInfo().constantFitsInImmedField(V9::STXi, Offset));
+ MI = BuildMI(V9::STXi,3).addMReg(SrcReg).addMReg(DestPtrReg)
+ .addSImm(Offset);
break;
case FPSingleRegType:
- MI = new MachineInstr(ST, 3);
- MI->SetMachineOperandReg(0, SrcReg, false);
- MI->SetMachineOperandReg(1, DestPtrReg, false);
- MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed,
- (int64_t) Offset);
- mvec.push_back(MI);
+ assert(target.getInstrInfo().constantFitsInImmedField(V9::STFi, Offset));
+ MI = BuildMI(V9::STFi, 3).addMReg(SrcReg).addMReg(DestPtrReg)
+ .addSImm(Offset);
break;
case FPDoubleRegType:
- MI = new MachineInstr(STD, 3);
- MI->SetMachineOperandReg(0, SrcReg, false);
- MI->SetMachineOperandReg(1, DestPtrReg, false);
- MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed,
- (int64_t) Offset);
- mvec.push_back(MI);
+ assert(target.getInstrInfo().constantFitsInImmedField(V9::STDFi, Offset));
+ MI = BuildMI(V9::STDFi,3).addMReg(SrcReg).addMReg(DestPtrReg)
+ .addSImm(Offset);
break;
case IntCCRegType:
assert(getRegType(scratchReg) ==IntRegType && "Invalid scratch reg");
// Use SrcReg+1 to get the name "%ccr" instead of "%xcc" for RDCCR
- MI = Create2OperandInstr_Reg(RDCCR, SrcReg+1, scratchReg);
+ MI = BuildMI(V9::RDCCR, 2).addMReg(SrcReg+1).addMReg(scratchReg, MOTy::Def);
mvec.push_back(MI);
cpReg2MemMI(mvec, scratchReg, DestPtrReg, Offset, IntRegType);
- break;
+ return;
- case FloatCCRegType:
- assert(0 && "Tell Vikram if this assertion fails: we may have to mask out the other bits here");
- MI = new MachineInstr(STXFSR, 3);
- MI->SetMachineOperandReg(0, SrcReg, false);
- MI->SetMachineOperandReg(1, DestPtrReg, false);
- MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed,
- (int64_t) Offset);
- mvec.push_back(MI);
+ case FloatCCRegType: {
+ assert(target.getInstrInfo().constantFitsInImmedField(V9::STXFSRi, Offset));
+ unsigned fsrRegNum = getUnifiedRegNum(UltraSparcRegInfo::SpecialRegClassID,
+ SparcSpecialRegClass::fsr);
+ MI = BuildMI(V9::STXFSRi, 3)
+ .addMReg(fsrRegNum).addMReg(DestPtrReg).addSImm(Offset);
break;
-
+ }
default:
assert(0 && "Unknown RegType in cpReg2MemMI");
}
+ mvec.push_back(MI);
}
void
-UltraSparcRegInfo::cpMem2RegMI(vector<MachineInstr*>& mvec,
+UltraSparcRegInfo::cpMem2RegMI(std::vector<MachineInstr*>& mvec,
unsigned SrcPtrReg,
int Offset,
unsigned DestReg,
MachineInstr * MI = NULL;
switch (RegType) {
case IntRegType:
- MI = new MachineInstr(LDX, 3);
- MI->SetMachineOperandReg(0, SrcPtrReg, false);
- MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed,
- (int64_t) Offset);
- MI->SetMachineOperandReg(2, DestReg, true);
- mvec.push_back(MI);
+ assert(target.getInstrInfo().constantFitsInImmedField(V9::LDXi, Offset));
+ MI = BuildMI(V9::LDXi, 3).addMReg(SrcPtrReg).addSImm(Offset)
+ .addMReg(DestReg, MOTy::Def);
break;
case FPSingleRegType:
- MI = new MachineInstr(LD, 3);
- MI->SetMachineOperandReg(0, SrcPtrReg, false);
- MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed,
- (int64_t) Offset);
- MI->SetMachineOperandReg(2, DestReg, true);
- mvec.push_back(MI);
+ assert(target.getInstrInfo().constantFitsInImmedField(V9::LDFi, Offset));
+ MI = BuildMI(V9::LDFi, 3).addMReg(SrcPtrReg).addSImm(Offset)
+ .addMReg(DestReg, MOTy::Def);
break;
case FPDoubleRegType:
- MI = new MachineInstr(LDD, 3);
- MI->SetMachineOperandReg(0, SrcPtrReg, false);
- MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed,
- (int64_t) Offset);
- MI->SetMachineOperandReg(2, DestReg, true);
- mvec.push_back(MI);
+ assert(target.getInstrInfo().constantFitsInImmedField(V9::LDDFi, Offset));
+ MI = BuildMI(V9::LDDFi, 3).addMReg(SrcPtrReg).addSImm(Offset)
+ .addMReg(DestReg, MOTy::Def);
break;
case IntCCRegType:
cpMem2RegMI(mvec, SrcPtrReg, Offset, scratchReg, IntRegType);
// Use DestReg+1 to get the name "%ccr" instead of "%xcc" for WRCCR
- MI = Create2OperandInstr_Reg(WRCCR, scratchReg, DestReg+1);
- mvec.push_back(MI);
-
+ MI = BuildMI(V9::WRCCRr, 3).addMReg(scratchReg)
+ .addMReg(SparcIntRegClass::g0).addMReg(DestReg+1,MOTy::Def);
break;
- case FloatCCRegType:
- assert(0 && "Tell Vikram if this assertion fails: we may have to mask out the other bits here");
- MI = new MachineInstr(LDXFSR, 3);
- MI->SetMachineOperandReg(0, SrcPtrReg, false);
- MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed,
- (int64_t) Offset);
- MI->SetMachineOperandReg(2, DestReg, true);
- mvec.push_back(MI);
+ case FloatCCRegType: {
+ assert(target.getInstrInfo().constantFitsInImmedField(V9::LDXFSRi, Offset));
+ unsigned fsrRegNum = getUnifiedRegNum(UltraSparcRegInfo::SpecialRegClassID,
+ SparcSpecialRegClass::fsr);
+ MI = BuildMI(V9::LDXFSRi, 3).addMReg(SrcPtrReg).addSImm(Offset)
+ .addMReg(fsrRegNum, MOTy::UseAndDef);
break;
-
+ }
default:
assert(0 && "Unknown RegType in cpMem2RegMI");
}
+ mvec.push_back(MI);
}
void
-UltraSparcRegInfo::cpValue2Value(Value *Src,
- Value *Dest,
- vector<MachineInstr*>& mvec) const {
- int RegType = getRegType( Src );
-
- assert( (RegType==getRegType(Src)) && "Src & Dest are diff types");
-
+UltraSparcRegInfo::cpValue2Value(Value *Src, Value *Dest,
+ std::vector<MachineInstr*>& mvec) const {
+ int RegType = getRegType(Src->getType());
MachineInstr * MI = NULL;
switch( RegType ) {
case IntRegType:
- MI = new MachineInstr(ADD, 3);
- MI->SetMachineOperandVal(0, MachineOperand:: MO_VirtualRegister, Src, false);
- MI->SetMachineOperandReg(1, getZeroRegNum(), false);
- MI->SetMachineOperandVal(2, MachineOperand:: MO_VirtualRegister, Dest, true);
+ MI = BuildMI(V9::ADDr, 3).addReg(Src).addMReg(getZeroRegNum())
+ .addRegDef(Dest);
break;
-
case FPSingleRegType:
- MI = new MachineInstr(FMOVS, 2);
- MI->SetMachineOperandVal(0, MachineOperand:: MO_VirtualRegister, Src, false);
- MI->SetMachineOperandVal(1, MachineOperand:: MO_VirtualRegister, Dest, true);
+ MI = BuildMI(V9::FMOVS, 2).addReg(Src).addRegDef(Dest);
break;
-
-
case FPDoubleRegType:
- MI = new MachineInstr(FMOVD, 2);
- MI->SetMachineOperandVal(0, MachineOperand:: MO_VirtualRegister, Src, false);
- MI->SetMachineOperandVal(1, MachineOperand:: MO_VirtualRegister, Dest, true);
+ MI = BuildMI(V9::FMOVD, 2).addReg(Src).addRegDef(Dest);
break;
-
default:
assert(0 && "Unknow RegType in CpValu2Value");
}
- if (MI)
- mvec.push_back(MI);
+ mvec.push_back(MI);
}
void
-UltraSparcRegInfo::insertCallerSavingCode(vector<MachineInstr*>& instrnsBefore,
- vector<MachineInstr*>& instrnsAfter,
- MachineInstr *CallMI,
- const BasicBlock *BB,
- PhyRegAlloc &PRA) const
+UltraSparcRegInfo::insertCallerSavingCode
+(std::vector<MachineInstr*> &instrnsBefore,
+ std::vector<MachineInstr*> &instrnsAfter,
+ MachineInstr *CallMI,
+ const BasicBlock *BB,
+ PhyRegAlloc &PRA) const
{
- assert ( (UltraSparcInfo->getInstrInfo()).isCall(CallMI->getOpCode()) );
+ assert ( (target.getInstrInfo()).isCall(CallMI->getOpCode()) );
// has set to record which registers were saved/restored
//
CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
- // Now find the LR of the return value of the call
- // The last *implicit operand* is the return value of a call
- // Insert it to to he PushedRegSet since we must not save that register
+ // Now check if the call has a return value (using argDesc) and if so,
+ // find the LR of the TmpInstruction representing the return value register.
+ // (using the last or second-last *implicit operand* of the call MI).
+ // Insert it to to the PushedRegSet since we must not save that register
// and restore it after the call.
// We do this because, we look at the LV set *after* the instruction
// to determine, which LRs must be saved across calls. The return value
// of the call is live in this set - but we must not save/restore it.
-
- const Value *RetVal = argDesc->getReturnValue();
-
- if (RetVal) {
- LiveRange *RetValLR = PRA.LRI.getLiveRangeForValue( RetVal );
+ //
+ if (const Value *origRetVal = argDesc->getReturnValue()) {
+ unsigned retValRefNum = (CallMI->getNumImplicitRefs() -
+ (argDesc->getIndirectFuncPtr()? 1 : 2));
+ const TmpInstruction* tmpRetVal =
+ cast<TmpInstruction>(CallMI->getImplicitRef(retValRefNum));
+ assert(tmpRetVal->getOperand(0) == origRetVal &&
+ tmpRetVal->getType() == origRetVal->getType() &&
+ "Wrong implicit ref?");
+ LiveRange *RetValLR = PRA.LRI.getLiveRangeForValue( tmpRetVal );
assert(RetValLR && "No LR for RetValue of call");
if (RetValLR->hasColor())
- PushedRegSet.insert(
- getUnifiedRegNum((RetValLR->getRegClass())->getID(),
- RetValLR->getColor() ) );
+ PushedRegSet.insert(getUnifiedRegNum(RetValLR->getRegClassID(),
+ RetValLR->getColor()));
}
const ValueSet &LVSetAft = PRA.LVI->getLiveVarSetAfterMInst(CallMI, BB);
if( LR->hasColor() ) {
- unsigned RCID = (LR->getRegClass())->getID();
+ unsigned RCID = LR->getRegClassID();
unsigned Color = LR->getColor();
if ( isRegVolatile(RCID, Color) ) {
// if we haven't already pushed that register
- unsigned RegType = getRegType( LR );
+ unsigned RegType = getRegType(LR);
// Now get two instructions - to push on stack and pop from stack
// and add them to InstrnsBefore and InstrnsAfter of the
// call instruction
//
- int StackOff = PRA.mcInfo.pushTempValue(target,
- getSpilledRegSize(RegType));
-
- vector<MachineInstr*> AdIBef, AdIAft;
+ int StackOff =
+ PRA.MF.getInfo()->pushTempValue(getSpilledRegSize(RegType));
//---- Insert code for pushing the reg on stack ----------
+ std::vector<MachineInstr*> AdIBef, AdIAft;
+
// We may need a scratch register to copy the saved value
// to/from memory. This may itself have to insert code to
// free up a scratch register. Any such code should go before
- // the save code.
+ // the save code. The scratch register, if any, is by default
+ // temporary and not "used" by the instruction unless the
+ // copy code itself decides to keep the value in the scratch reg.
int scratchRegType = -1;
int scratchReg = -1;
if (regTypeNeedsScratchReg(RegType, scratchRegType))
scratchReg = PRA.getUsableUniRegAtMI(scratchRegType, &LVSetBef,
CallMI, AdIBef, AdIAft);
assert(scratchReg != getInvalidRegNum());
- CallMI->getRegsUsed().insert(scratchReg);
}
if (AdIBef.size() > 0)
//---- Insert code for popping the reg from the stack ----------
+ AdIBef.clear();
+ AdIAft.clear();
+
// We may need a scratch register to copy the saved value
// from memory. This may itself have to insert code to
// free up a scratch register. Any such code should go
- // after the save code.
+ // after the save code. As above, scratch is not marked "used".
//
scratchRegType = -1;
scratchReg = -1;
scratchReg = PRA.getUsableUniRegAtMI(scratchRegType, &LVSetAft,
CallMI, AdIBef, AdIAft);
assert(scratchReg != getInvalidRegNum());
- CallMI->getRegsUsed().insert(scratchReg);
}
if (AdIBef.size() > 0)
PushedRegSet.insert(Reg);
if(DEBUG_RA) {
- cerr << "\nFor call inst:" << *CallMI;
- cerr << " -inserted caller saving instrs: Before:\n\t ";
+ std::cerr << "\nFor call inst:" << *CallMI;
+ std::cerr << " -inserted caller saving instrs: Before:\n\t ";
for_each(instrnsBefore.begin(), instrnsBefore.end(),
std::mem_fun(&MachineInstr::dump));
- cerr << " -and After:\n\t ";
+ std::cerr << " -and After:\n\t ";
for_each(instrnsAfter.begin(), instrnsAfter.end(),
std::mem_fun(&MachineInstr::dump));
}
// Print the register assigned to a LR
//---------------------------------------------------------------------------
-void UltraSparcRegInfo::printReg(const LiveRange *LR) {
- unsigned RegClassID = (LR->getRegClass())->getID();
- cerr << " *Node " << (LR->getUserIGNode())->getIndex();
+void UltraSparcRegInfo::printReg(const LiveRange *LR) const {
+ unsigned RegClassID = LR->getRegClassID();
+ std::cerr << " *Node " << (LR->getUserIGNode())->getIndex();
if (!LR->hasColor()) {
- cerr << " - could not find a color\n";
+ std::cerr << " - could not find a color\n";
return;
}
// if a color is found
- cerr << " colored with color "<< LR->getColor();
-
- if (RegClassID == IntRegClassID) {
- cerr<< " [" << SparcIntRegClass::getRegName(LR->getColor()) << "]\n";
+ std::cerr << " colored with color "<< LR->getColor();
- } else if (RegClassID == FloatRegClassID) {
- cerr << "[" << SparcFloatRegClass::getRegName(LR->getColor());
- if( LR->getType() == Type::DoubleTy)
- cerr << "+" << SparcFloatRegClass::getRegName(LR->getColor()+1);
- cerr << "]\n";
- }
+ unsigned uRegName = getUnifiedRegNum(RegClassID, LR->getColor());
+
+ std::cerr << "[";
+ std::cerr<< getUnifiedRegName(uRegName);
+ if (RegClassID == FloatRegClassID && LR->getType() == Type::DoubleTy)
+ std::cerr << "+" << getUnifiedRegName(uRegName+1);
+ std::cerr << "]\n";
}
//---------------------------------------------------------------------------
do {
CouldMoveAll = true;
- std::vector<MachineInstr *>::iterator DefIt = UnordVec.begin();
+ std::vector<MachineInstr*>::iterator DefIt = UnordVec.begin();
for( ; DefIt != UnordVec.end(); ++DefIt ) {
if( DefInst == NULL) continue;
- //cerr << "\nInst in UnordVec = " << *DefInst;
+ //std::cerr << "\nInst in UnordVec = " << *DefInst;
// last operand is the def (unless for a store which has no def reg)
MachineOperand& DefOp = DefInst->getOperand(DefInst->getNumOperands()-1);
- if( DefOp.opIsDef() &&
- DefOp.getOperandType() == MachineOperand::MO_MachineRegister) {
+ if ((DefOp.opIsDefOnly() || DefOp.opIsDefAndUse()) &&
+ DefOp.getType() == MachineOperand::MO_MachineRegister) {
// If the operand in DefInst is a def ...
-
bool DefEqUse = false;
- std::vector<MachineInstr *>::iterator UseIt = DefIt;
+ std::vector<MachineInstr*>::iterator UseIt = DefIt;
UseIt++;
for( ; UseIt != UnordVec.end(); ++UseIt ) {
// for each inst (UseInst) that is below the DefInst do ...
MachineOperand& UseOp = UseInst->getOperand(0);
- if( ! UseOp.opIsDef() &&
- UseOp.getOperandType() == MachineOperand::MO_MachineRegister) {
+ if (!UseOp.opIsDefOnly() &&
+ UseOp.getType() == MachineOperand::MO_MachineRegister) {
// if use is a register ...
// if Def and this use are the same, it means that this use
// is destroyed by a def before it is used
- // cerr << "\nCouldn't move " << *DefInst;
+ // std::cerr << "\nCouldn't move " << *DefInst;
DefEqUse = true;
CouldMoveAll = false;
// after examining all the instructions that follow the DefInst
// if there are no dependencies, we can move it to the OrdVec
- // cerr << "Moved to Ord: " << *DefInst;
+ // std::cerr << "Moved to Ord: " << *DefInst;
moveInst2OrdVec(OrdVec, DefInst, PRA);
} while(!CouldMoveAll);
if (DebugPrint && DEBUG_RA) {
- cerr << "\nAdded instructions were reordered to:\n";
- for(unsigned int i=0; i < OrdVec.size(); i++)
- cerr << *(OrdVec[i]);
+ std::cerr << "\nAdded instructions were reordered to:\n";
+ for(unsigned i=0; i < OrdVec.size(); i++)
+ std::cerr << *OrdVec[i];
}
}
-void UltraSparcRegInfo::moveInst2OrdVec(std::vector<MachineInstr *> &OrdVec,
+void UltraSparcRegInfo::moveInst2OrdVec(std::vector<MachineInstr*> &OrdVec,
MachineInstr *UnordInst,
PhyRegAlloc &PRA) const {
MachineOperand& UseOp = UnordInst->getOperand(0);
- if( ! UseOp.opIsDef() &&
- UseOp.getOperandType() == MachineOperand::MO_MachineRegister) {
+ if (!UseOp.opIsDefOnly() &&
+ UseOp.getType() == MachineOperand::MO_MachineRegister) {
// for the use of UnordInst, see whether there is a defining instr
// before in the OrdVec
bool DefEqUse = false;
- std::vector<MachineInstr *>::iterator OrdIt = OrdVec.begin();
+ std::vector<MachineInstr*>::iterator OrdIt = OrdVec.begin();
for( ; OrdIt != OrdVec.end(); ++OrdIt ) {
MachineOperand& DefOp =
OrdInst->getOperand(OrdInst->getNumOperands()-1);
- if( DefOp.opIsDef() &&
- DefOp.getOperandType() == MachineOperand::MO_MachineRegister) {
+ if( (DefOp.opIsDefOnly() || DefOp.opIsDefAndUse()) &&
+ DefOp.getType() == MachineOperand::MO_MachineRegister) {
- //cerr << "\nDefining Ord Inst: " << *OrdInst;
+ //std::cerr << "\nDefining Ord Inst: " << *OrdInst;
if( DefOp.getMachineRegNum() == UseOp.getMachineRegNum() ) {
// Now we are processing %ox of 1.
// We have to
- const int UReg = DefOp.getMachineRegNum();
- const int RegType = getRegType(UReg);
+ int UReg = DefOp.getMachineRegNum();
+ int RegType = getRegType(UReg);
MachineInstr *AdIBef, *AdIAft;
- const int StackOff = PRA.mcInfo.pushTempValue(target,
- getSpilledRegSize(RegType));
+ int StackOff =
+ PRA.MF.getInfo()->pushTempValue(getSpilledRegSize(RegType));
// Save the UReg (%ox) on stack before it's destroyed
- vector<MachineInstr*> mvec;
+ std::vector<MachineInstr*> mvec;
cpReg2MemMI(mvec, UReg, getFramePointer(), StackOff, RegType);
- for (vector<MachineInstr*>::iterator MI=mvec.begin(); MI != mvec.end(); ++MI) {
- OrdIt = OrdVec.insert(OrdIt, *MI);
- ++OrdIt; // OrdIt must still point to current instr we processed
- }
+ for (std::vector<MachineInstr*>::iterator MI=mvec.begin();
+ MI != mvec.end(); ++MI)
+ OrdIt = 1+OrdVec.insert(OrdIt, *MI);
// Load directly into DReg (%oy)
MachineOperand& DOp=
(UnordInst->getOperand(UnordInst->getNumOperands()-1));
- assert(DOp.opIsDef() && "Last operand is not the def");
+ assert((DOp.opIsDefOnly() || DefOp.opIsDefAndUse()) &&
+ "Last operand is not the def");
const int DReg = DOp.getMachineRegNum();
cpMem2RegMI(OrdVec, getFramePointer(), StackOff, DReg, RegType);
- cerr << "\nFixed CIRCULAR references by reordering";
-
if( DEBUG_RA ) {
- cerr << "\nBefore CIRCULAR Reordering:\n";
- cerr << *UnordInst;
- cerr << *OrdInst;
+ std::cerr << "\nFixed CIRCULAR references by reordering:";
+ std::cerr << "\nBefore CIRCULAR Reordering:\n";
+ std::cerr << *UnordInst;
+ std::cerr << *OrdInst;
- cerr << "\nAfter CIRCULAR Reordering - All Inst so far:\n";
+ std::cerr << "\nAfter CIRCULAR Reordering - All Inst so far:\n";
for(unsigned i=0; i < OrdVec.size(); i++)
- cerr << *(OrdVec[i]);
+ std::cerr << *(OrdVec[i]);
}
// Do not copy the UseInst to OrdVec
// We didn't find a def in the OrdVec, so just append this inst
OrdVec.push_back( UnordInst );
- //cerr << "Reordered Inst (Moved Dn): " << *UnordInst;
+ //std::cerr << "Reordered Inst (Moved Dn): " << *UnordInst;
}
}// if the operand in UnordInst is a use
projects / oota-llvm.git / blobdiff