-#include "llvm/CodeGen/LiveRangeInfo.h"
-#include "llvm/CodeGen/RegClass.h"
+//===-- LiveRangeInfo.cpp -------------------------------------------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// Live range construction for coloring-based register allocation for LLVM.
+//
+//===----------------------------------------------------------------------===//
+
+#include "IGNode.h"
+#include "LiveRangeInfo.h"
+#include "RegAllocCommon.h"
+#include "RegClass.h"
+#include "llvm/Function.h"
#include "llvm/CodeGen/MachineInstr.h"
-#include "llvm/CodeGen/MachineCodeForBasicBlock.h"
+#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Function.h"
-#include "llvm/BasicBlock.h"
+#include "llvm/Target/TargetInstrInfo.h"
+#include "../SparcV9RegInfo.h"
#include "Support/SetOperations.h"
-#include "llvm/CodeGen/RegAllocCommon.h"
-using std::cerr;
+
+namespace llvm {
+
+unsigned LiveRange::getRegClassID() const { return getRegClass()->getID(); }
LiveRangeInfo::LiveRangeInfo(const Function *F, const TargetMachine &tm,
std::vector<RegClass *> &RCL)
// live range. We have to make the other entries NULL when we delete
// a live range.
- for(LiveRange::iterator LI = LR->begin(); LI != LR->end(); ++LI)
+ for (LiveRange::iterator LI = LR->begin(); LI != LR->end(); ++LI)
LiveRangeMap[*LI] = 0;
delete LR;
void LiveRangeInfo::unionAndUpdateLRs(LiveRange *L1, LiveRange *L2) {
assert(L1 != L2 && (!L1->hasSuggestedColor() || !L2->hasSuggestedColor()));
+ assert(! (L1->hasColor() && L2->hasColor()) ||
+ L1->getColor() == L2->getColor());
+
set_union(*L1, *L2); // add elements of L2 to L1
for(ValueSet::iterator L2It = L2->begin(); L2It != L2->end(); ++L2It) {
LiveRangeMap[*L2It] = L1; // now the elements in L2 should map
//to L1
}
-
-
- // Now if LROfDef(L1) has a suggested color, it will remain.
- // But, if LROfUse(L2) has a suggested color, the new range
- // must have the same color.
-
- if(L2->hasSuggestedColor())
- L1->setSuggestedColor(L2->getSuggestedColor());
-
-
+
+ // set call interference for L1 from L2
if (L2->isCallInterference())
L1->setCallInterference();
// add the spill costs
L1->addSpillCost(L2->getSpillCost());
+
+ // If L2 has a color, give L1 that color. Note that L1 may have had the same
+ // color or none, but would not have a different color as asserted above.
+ if (L2->hasColor())
+ L1->setColor(L2->getColor());
+
+ // Similarly, if LROfUse(L2) has a suggested color, the new range
+ // must have the same color.
+ if (L2->hasSuggestedColor())
+ L1->setSuggestedColor(L2->getSuggestedColor());
delete L2; // delete L2 as it is no longer needed
}
+//---------------------------------------------------------------------------
+// Method for creating a single live range for a definition.
+// The definition must be represented by a virtual register (a Value).
+// Note: this function does *not* check that no live range exists for def.
+//---------------------------------------------------------------------------
+
+LiveRange*
+LiveRangeInfo::createNewLiveRange(const Value* Def, bool isCC /* = false*/)
+{
+ LiveRange* DefRange = new LiveRange(); // Create a new live range,
+ DefRange->insert(Def); // add Def to it,
+ LiveRangeMap[Def] = DefRange; // and update the map.
+
+ // set the register class of the new live range
+ DefRange->setRegClass(RegClassList[MRI.getRegClassIDOfType(Def->getType(),
+ isCC)]);
+
+ if (DEBUG_RA >= RA_DEBUG_LiveRanges) {
+ std::cerr << " Creating a LR for def ";
+ if (isCC) std::cerr << " (CC Register!)";
+ std::cerr << " : " << RAV(Def) << "\n";
+ }
+ return DefRange;
+}
+
+
+LiveRange*
+LiveRangeInfo::createOrAddToLiveRange(const Value* Def, bool isCC /* = false*/)
+{
+ LiveRange *DefRange = LiveRangeMap[Def];
+
+ // check if the LR is already there (because of multiple defs)
+ if (!DefRange) {
+ DefRange = createNewLiveRange(Def, isCC);
+ } else { // live range already exists
+ DefRange->insert(Def); // add the operand to the range
+ LiveRangeMap[Def] = DefRange; // make operand point to merged set
+ if (DEBUG_RA >= RA_DEBUG_LiveRanges)
+ std::cerr << " Added to existing LR for def: " << RAV(Def) << "\n";
+ }
+ return DefRange;
+}
+
//---------------------------------------------------------------------------
// Method for constructing all live ranges in a function. It creates live
//---------------------------------------------------------------------------
void LiveRangeInfo::constructLiveRanges() {
- if (DEBUG_RA)
- cerr << "Consturcting Live Ranges ...\n";
+ if (DEBUG_RA >= RA_DEBUG_LiveRanges)
+ std::cerr << "Constructing Live Ranges ...\n";
// first find the live ranges for all incoming args of the function since
// those LRs start from the start of the function
- for (Function::const_aiterator AI = Meth->abegin(); AI != Meth->aend(); ++AI){
- LiveRange *ArgRange = new LiveRange(); // creates a new LR and
- ArgRange->insert(AI); // add the arg (def) to it
- LiveRangeMap[AI] = ArgRange;
-
- // create a temp machine op to find the register class of value
- //const MachineOperand Op(MachineOperand::MO_VirtualRegister);
-
- unsigned rcid = MRI.getRegClassIDOfValue(AI);
- ArgRange->setRegClass(RegClassList[rcid]);
-
-
- if( DEBUG_RA > 1)
- cerr << " adding LiveRange for argument " << RAV(AI) << "\n";
- }
+ for (Function::const_aiterator AI = Meth->abegin(); AI != Meth->aend(); ++AI)
+ createNewLiveRange(AI, /*isCC*/ false);
// Now suggest hardware registers for these function args
MRI.suggestRegs4MethodArgs(Meth, *this);
-
- // Now find speical LLVM instructions (CALL, RET) and LRs in machine
- // instructions.
+ // Now create LRs for machine instructions. A new LR will be created
+ // only for defs in the machine instr since, we assume that all Values are
+ // defined before they are used. However, there can be multiple defs for
+ // the same Value in machine instructions.
+ //
+ // Also, find CALL and RETURN instructions, which need extra work.
//
- for (Function::const_iterator BBI=Meth->begin(); BBI != Meth->end(); ++BBI){
- // Now find all LRs for machine the instructions. A new LR will be created
- // only for defs in the machine instr since, we assume that all Values are
- // defined before they are used. However, there can be multiple defs for
- // the same Value in machine instructions.
-
- // get the iterator for machine instructions
- MachineCodeForBasicBlock& MIVec = MachineCodeForBasicBlock::get(BBI);
-
- // iterate over all the machine instructions in BB
- for(MachineCodeForBasicBlock::iterator MInstIterator = MIVec.begin();
- MInstIterator != MIVec.end(); ++MInstIterator) {
- MachineInstr *MInst = *MInstIterator;
-
- // Now if the machine instruction is a call/return instruction,
- // add it to CallRetInstrList for processing its implicit operands
+ MachineFunction &MF = MachineFunction::get(Meth);
+ for (MachineFunction::iterator BBI = MF.begin(); BBI != MF.end(); ++BBI) {
+ MachineBasicBlock &MBB = *BBI;
- if(TM.getInstrInfo().isReturn(MInst->getOpCode()) ||
- TM.getInstrInfo().isCall(MInst->getOpCode()))
- CallRetInstrList.push_back( MInst );
+ // iterate over all the machine instructions in BB
+ for(MachineBasicBlock::iterator MInstIterator = MBB.begin();
+ MInstIterator != MBB.end(); ++MInstIterator) {
+ MachineInstr *MInst = MInstIterator;
+
+ // If the machine instruction is a call/return instruction, add it to
+ // CallRetInstrList for processing its args, ret value, and ret addr.
+ //
+ if(TM.getInstrInfo().isReturn(MInst->getOpcode()) ||
+ TM.getInstrInfo().isCall(MInst->getOpcode()))
+ CallRetInstrList.push_back(MInst);
-
- // iterate over MI operands to find defs
+ // iterate over explicit MI operands and create a new LR
+ // for each operand that is defined by the instruction
for (MachineInstr::val_op_iterator OpI = MInst->begin(),
- OpE = MInst->end(); OpI != OpE; ++OpI) {
- if(DEBUG_RA) {
- MachineOperand::MachineOperandType OpTyp =
- OpI.getMachineOperand().getOperandType();
-
- if (OpTyp == MachineOperand::MO_CCRegister)
- cerr << "\n**CC reg found. Is Def=" << OpI.isDef() << " Val:"
- << RAV(OpI.getMachineOperand().getVRegValue()) << "\n";
- }
-
- // create a new LR iff this operand is a def
+ OpE = MInst->end(); OpI != OpE; ++OpI)
if (OpI.isDef()) {
const Value *Def = *OpI;
+ bool isCC = (OpI.getMachineOperand().getType()
+ == MachineOperand::MO_CCRegister);
+ LiveRange* LR = createOrAddToLiveRange(Def, isCC);
+
+ // If the operand has a pre-assigned register,
+ // set it directly in the LiveRange
+ if (OpI.getMachineOperand().hasAllocatedReg()) {
+ unsigned getClassId;
+ LR->setColor(MRI.getClassRegNum(OpI.getMachineOperand().getReg(),
+ getClassId));
+ }
+ }
- // Only instruction values are accepted for live ranges here
- if (Def->getValueType() != Value::InstructionVal ) {
- cerr << "\n**%%Error: Def is not an instruction val. Def="
- << RAV(Def) << "\n";
- continue;
- }
-
- LiveRange *DefRange = LiveRangeMap[Def];
-
- // see LR already there (because of multiple defs)
- if( !DefRange) { // if it is not in LiveRangeMap
- DefRange = new LiveRange(); // creates a new live range and
- DefRange->insert(Def); // add the instruction (def) to it
- LiveRangeMap[ Def ] = DefRange; // update the map
-
- if (DEBUG_RA > 1)
- cerr << " creating a LR for def: " << RAV(Def) << "\n";
-
- // set the register class of the new live range
- //assert( RegClassList.size() );
- MachineOperand::MachineOperandType OpTy =
- OpI.getMachineOperand().getOperandType();
-
- bool isCC = ( OpTy == MachineOperand::MO_CCRegister);
- unsigned rcid = MRI.getRegClassIDOfValue(
- OpI.getMachineOperand().getVRegValue(), isCC );
-
-
- if (isCC && DEBUG_RA)
- cerr << "\a**created a LR for a CC reg:"
- << RAV(OpI.getMachineOperand().getVRegValue());
-
- DefRange->setRegClass(RegClassList[rcid]);
- } else {
- DefRange->insert(Def); // add the opearand to def range
- // update the map - Operand points
- // to the merged set
- LiveRangeMap[Def] = DefRange;
-
- if (DEBUG_RA > 1)
- cerr << " added to an existing LR for def: "
- << RAV(Def) << "\n";
- }
-
- } // if isDef()
-
- } // for all opereands in machine instructions
+ // iterate over implicit MI operands and create a new LR
+ // for each operand that is defined by the instruction
+ for (unsigned i = 0; i < MInst->getNumImplicitRefs(); ++i)
+ if (MInst->getImplicitOp(i).isDef()) {
+ const Value *Def = MInst->getImplicitRef(i);
+ LiveRange* LR = createOrAddToLiveRange(Def, /*isCC*/ false);
+
+ // If the implicit operand has a pre-assigned register,
+ // set it directly in the LiveRange
+ if (MInst->getImplicitOp(i).hasAllocatedReg()) {
+ unsigned getClassId;
+ LR->setColor(MRI.getClassRegNum(
+ MInst->getImplicitOp(i).getReg(),
+ getClassId));
+ }
+ }
} // for all machine instructions in the BB
-
} // for all BBs in function
-
// Now we have to suggest clors for call and return arg live ranges.
// Also, if there are implicit defs (e.g., retun value of a call inst)
// they must be added to the live range list
-
+ //
suggestRegs4CallRets();
- if( DEBUG_RA)
- cerr << "Initial Live Ranges constructed!\n";
-
+ if( DEBUG_RA >= RA_DEBUG_LiveRanges)
+ std::cerr << "Initial Live Ranges constructed!\n";
}
// 1) suggest colors for call and return args.
// 2) create new LRs for implicit defs in machine instructions
//---------------------------------------------------------------------------
-void LiveRangeInfo::suggestRegs4CallRets()
-{
- CallRetInstrListType::iterator It = CallRetInstrList.begin();
- for( ; It != CallRetInstrList.end(); ++It ) {
-
+void LiveRangeInfo::suggestRegs4CallRets() {
+ std::vector<MachineInstr*>::iterator It = CallRetInstrList.begin();
+ for( ; It != CallRetInstrList.end(); ++It) {
MachineInstr *MInst = *It;
- MachineOpCode OpCode = MInst->getOpCode();
-
- if( (TM.getInstrInfo()).isReturn(OpCode) )
- MRI.suggestReg4RetValue( MInst, *this);
+ MachineOpCode OpCode = MInst->getOpcode();
- else if( (TM.getInstrInfo()).isCall( OpCode ) )
- MRI.suggestRegs4CallArgs( MInst, *this, RegClassList );
-
+ if ((TM.getInstrInfo()).isReturn(OpCode))
+ MRI.suggestReg4RetValue(MInst, *this);
+ else if ((TM.getInstrInfo()).isCall(OpCode))
+ MRI.suggestRegs4CallArgs(MInst, *this);
else
- assert( 0 && "Non call/ret instr in CallRetInstrList" );
+ assert( 0 && "Non call/ret instr in CallRetInstrList" );
}
-
}
*/
//---------------------------------------------------------------------------
+
+
+// Checks if live range LR interferes with any node assigned or suggested to
+// be assigned the specified color
+//
+inline bool InterferesWithColor(const LiveRange& LR, unsigned color) {
+ IGNode* lrNode = LR.getUserIGNode();
+ for (unsigned n=0, NN = lrNode->getNumOfNeighbors(); n < NN; n++) {
+ LiveRange *neighLR = lrNode->getAdjIGNode(n)->getParentLR();
+ if (neighLR->hasColor() && neighLR->getColor() == color)
+ return true;
+ if (neighLR->hasSuggestedColor() && neighLR->getSuggestedColor() == color)
+ return true;
+ }
+ return false;
+}
+
+// Cannot coalesce if any of the following is true:
+// (1) Both LRs have suggested colors (should be "different suggested colors"?)
+// (2) Both LR1 and LR2 have colors and the colors are different
+// (but if the colors are the same, it is definitely safe to coalesce)
+// (3) LR1 has color and LR2 interferes with any LR that has the same color
+// (4) LR2 has color and LR1 interferes with any LR that has the same color
+//
+inline bool InterfsPreventCoalescing(const LiveRange& LROfDef,
+ const LiveRange& LROfUse) {
+ // (4) if they have different suggested colors, cannot coalesce
+ if (LROfDef.hasSuggestedColor() && LROfUse.hasSuggestedColor())
+ return true;
+
+ // if neither has a color, nothing more to do.
+ if (! LROfDef.hasColor() && ! LROfUse.hasColor())
+ return false;
+
+ // (2, 3) if L1 has color...
+ if (LROfDef.hasColor()) {
+ if (LROfUse.hasColor())
+ return (LROfUse.getColor() != LROfDef.getColor());
+ return InterferesWithColor(LROfUse, LROfDef.getColor());
+ }
+
+ // (4) else only LROfUse has a color: check if that could interfere
+ return InterferesWithColor(LROfDef, LROfUse.getColor());
+}
+
+
void LiveRangeInfo::coalesceLRs()
{
- if(DEBUG_RA)
- cerr << "\nCoalscing LRs ...\n";
-
- for(Function::const_iterator BBI = Meth->begin(), BBE = Meth->end();
- BBI != BBE; ++BBI) {
+ if(DEBUG_RA >= RA_DEBUG_LiveRanges)
+ std::cerr << "\nCoalescing LRs ...\n";
- // get the iterator for machine instructions
- const MachineCodeForBasicBlock& MIVec = MachineCodeForBasicBlock::get(BBI);
- MachineCodeForBasicBlock::const_iterator MInstIterator = MIVec.begin();
+ MachineFunction &MF = MachineFunction::get(Meth);
+ for (MachineFunction::iterator BBI = MF.begin(); BBI != MF.end(); ++BBI) {
+ MachineBasicBlock &MBB = *BBI;
// iterate over all the machine instructions in BB
- for( ; MInstIterator != MIVec.end(); ++MInstIterator) {
-
- const MachineInstr * MInst = *MInstIterator;
+ for(MachineBasicBlock::iterator MII = MBB.begin(); MII != MBB.end(); ++MII){
+ const MachineInstr *MI = MII;
- if( DEBUG_RA > 1) {
- cerr << " *Iterating over machine instr ";
- MInst->dump();
- cerr << "\n";
+ if( DEBUG_RA >= RA_DEBUG_LiveRanges) {
+ std::cerr << " *Iterating over machine instr ";
+ MI->dump();
+ std::cerr << "\n";
}
-
// iterate over MI operands to find defs
- for(MachineInstr::const_val_op_iterator DefI = MInst->begin(),
- DefE = MInst->end(); DefI != DefE; ++DefI) {
- if (DefI.isDef()) { // iff this operand is a def
+ for(MachineInstr::const_val_op_iterator DefI = MI->begin(),
+ DefE = MI->end(); DefI != DefE; ++DefI) {
+ if (DefI.isDef()) { // this operand is modified
LiveRange *LROfDef = getLiveRangeForValue( *DefI );
RegClass *RCOfDef = LROfDef->getRegClass();
- MachineInstr::const_val_op_iterator UseI = MInst->begin(),
- UseE = MInst->end();
- for( ; UseI != UseE; ++UseI){ // for all uses
-
+ MachineInstr::const_val_op_iterator UseI = MI->begin(),
+ UseE = MI->end();
+ for( ; UseI != UseE; ++UseI) { // for all uses
LiveRange *LROfUse = getLiveRangeForValue( *UseI );
if (!LROfUse) { // if LR of use is not found
//don't warn about labels
- if (!isa<BasicBlock>(*UseI) && DEBUG_RA)
- cerr << " !! Warning: No LR for use " << RAV(*UseI) << "\n";
+ if (!isa<BasicBlock>(*UseI) && DEBUG_RA >= RA_DEBUG_LiveRanges)
+ std::cerr << " !! Warning: No LR for use " << RAV(*UseI)<< "\n";
continue; // ignore and continue
}
if (LROfUse == LROfDef) // nothing to merge if they are same
continue;
- if (MRI.getRegType(LROfDef) == MRI.getRegType(LROfUse)) {
-
+ if (MRI.getRegTypeForLR(LROfDef) ==
+ MRI.getRegTypeForLR(LROfUse)) {
// If the two RegTypes are the same
if (!RCOfDef->getInterference(LROfDef, LROfUse) ) {
LROfDef->getUserIGNode()->getNumOfNeighbors() +
LROfUse->getUserIGNode()->getNumOfNeighbors();
+ if (CombinedDegree > RCOfDef->getNumOfAvailRegs()) {
+ // get more precise estimate of combined degree
+ CombinedDegree = LROfDef->getUserIGNode()->
+ getCombinedDegree(LROfUse->getUserIGNode());
+ }
+
if (CombinedDegree <= RCOfDef->getNumOfAvailRegs()) {
- // if both LRs do not have suggested colors
- if (!(LROfDef->hasSuggestedColor() &&
- LROfUse->hasSuggestedColor())) {
-
+ // if both LRs do not have different pre-assigned colors
+ // and both LRs do not have suggested colors
+ if (! InterfsPreventCoalescing(*LROfDef, *LROfUse)) {
RCOfDef->mergeIGNodesOfLRs(LROfDef, LROfUse);
unionAndUpdateLRs(LROfDef, LROfUse);
}
} // for all machine instructions
} // for all BBs
- if (DEBUG_RA)
- cerr << "\nCoalscing Done!\n";
+ if (DEBUG_RA >= RA_DEBUG_LiveRanges)
+ std::cerr << "\nCoalescing Done!\n";
}
-
-
-
-
/*--------------------------- Debug code for printing ---------------*/
void LiveRangeInfo::printLiveRanges() {
LiveRangeMapType::iterator HMI = LiveRangeMap.begin(); // hash map iterator
- cerr << "\nPrinting Live Ranges from Hash Map:\n";
+ std::cerr << "\nPrinting Live Ranges from Hash Map:\n";
for( ; HMI != LiveRangeMap.end(); ++HMI) {
if (HMI->first && HMI->second) {
- cerr << " " << RAV(HMI->first) << "\t: ";
- printSet(*HMI->second); cerr << "\n";
+ std::cerr << " Value* " << RAV(HMI->first) << "\t: ";
+ if (IGNode* igNode = HMI->second->getUserIGNode())
+ std::cerr << "LR# " << igNode->getIndex();
+ else
+ std::cerr << "LR# " << "<no-IGNode>";
+ std::cerr << "\t:Values = "; printSet(*HMI->second); std::cerr << "\n";
}
}
}
+
+} // End llvm namespace
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