// Method: SchedGraphNode Destructor
//
// Description:
-// Free memory allocated by the SchedGraphNode object.
+// Free memory allocated by the SchedGraphNode object.
//
// Notes:
-// Do not delete the edges here. The base class will take care of that.
-// Only handle subclass specific stuff here (where currently there is
-// none).
+// Do not delete the edges here. The base class will take care of that.
+// Only handle subclass specific stuff here (where currently there is
+// none).
//
SchedGraphNode::~SchedGraphNode() {
}
// Method: SchedGraph Destructor
//
// Description:
-// This method deletes memory allocated by the SchedGraph object.
+// This method deletes memory allocated by the SchedGraph object.
//
// Notes:
-// Do not delete the graphRoot or graphLeaf here. The base class handles
-// that bit of work.
+// Do not delete the graphRoot or graphLeaf here. The base class handles
+// that bit of work.
//
SchedGraph::~SchedGraph() {
for (const_iterator I = begin(); I != end(); ++I)
void SchedGraph::addCDEdges(const TerminatorInst* term,
- const TargetMachine& target) {
+ const TargetMachine& target) {
const TargetInstrInfo& mii = *target.getInstrInfo();
MachineCodeForInstruction &termMvec = MachineCodeForInstruction::get(term);
! mii.isReturn(termMvec[first]->getOpcode()))
++first;
assert(first < termMvec.size() &&
- "No branch instructions for terminator? Ok, but weird!");
+ "No branch instructions for terminator? Ok, but weird!");
if (first == termMvec.size())
return;
assert(brNode && "No node for instr generated for branch/ret?");
(void) new SchedGraphEdge(brNode, toNode, SchedGraphEdge::CtrlDep,
SchedGraphEdge::NonDataDep, 0);
- break; // only one incoming edge is enough
+ break; // only one incoming edge is enough
}
}
SchedGraphNode* fromNode = getGraphNodeForInstr(I);
if (fromNode == NULL)
- continue; // dummy instruction, e.g., PHI
+ continue; // dummy instruction, e.g., PHI
(void) new SchedGraphEdge(fromNode, firstBrNode,
SchedGraphEdge::CtrlDep,
// latency does not otherwise matter (true dependences enforce that).
//
void SchedGraph::addMemEdges(const std::vector<SchedGraphNode*>& memNodeVec,
- const TargetMachine& target) {
+ const TargetMachine& target) {
const TargetInstrInfo& mii = *target.getInstrInfo();
// Instructions in memNodeVec are in execution order within the basic block,
// like with control dependences.
//
void SchedGraph::addCallDepEdges(const std::vector<SchedGraphNode*>& callDepNodeVec,
- const TargetMachine& target) {
+ const TargetMachine& target) {
const TargetInstrInfo& mii = *target.getInstrInfo();
// Instructions in memNodeVec are in execution order within the basic block,
if (mii.isCall(callDepNodeVec[ic]->getOpcode())) {
// Add SG_CALL_REF edges from all preds to this instruction.
for (unsigned jc=0; jc < ic; jc++)
- (void) new SchedGraphEdge(callDepNodeVec[jc], callDepNodeVec[ic],
- SchedGraphEdge::MachineRegister,
- MachineIntRegsRID, 0);
+ (void) new SchedGraphEdge(callDepNodeVec[jc], callDepNodeVec[ic],
+ SchedGraphEdge::MachineRegister,
+ MachineIntRegsRID, 0);
// And do the same from this instruction to all successors.
for (unsigned jc=ic+1; jc < NC; jc++)
- (void) new SchedGraphEdge(callDepNodeVec[ic], callDepNodeVec[jc],
- SchedGraphEdge::MachineRegister,
- MachineIntRegsRID, 0);
+ (void) new SchedGraphEdge(callDepNodeVec[ic], callDepNodeVec[jc],
+ SchedGraphEdge::MachineRegister,
+ MachineIntRegsRID, 0);
}
#ifdef CALL_DEP_NODE_VEC_CANNOT_WORK
void SchedGraph::addMachineRegEdges(RegToRefVecMap& regToRefVecMap,
- const TargetMachine& target) {
+ const TargetMachine& target) {
// This code assumes that two registers with different numbers are
// not aliased!
//
new SchedGraphEdge(prevNode, node, regNum,
SchedGraphEdge::AntiDep);
}
-
+
if (prevIsDef)
if (!isDef || isDefAndUse)
new SchedGraphEdge(prevNode, node, regNum,
// We do not consider other uses because we are not building use-use deps.
//
void SchedGraph::addEdgesForValue(SchedGraphNode* refNode,
- const RefVec& defVec,
- const Value* defValue,
- bool refNodeIsDef,
- bool refNodeIsUse,
- const TargetMachine& target) {
+ const RefVec& defVec,
+ const Value* defValue,
+ bool refNodeIsDef,
+ bool refNodeIsUse,
+ const TargetMachine& target) {
// Add true or output dep edges from all def nodes before refNode in BB.
// Add anti or output dep edges to all def nodes after refNode.
for (RefVec::const_iterator I=defVec.begin(), E=defVec.end(); I != E; ++I) {
void SchedGraph::addEdgesForInstruction(const MachineInstr& MI,
- const ValueToDefVecMap& valueToDefVecMap,
- const TargetMachine& target) {
+ const ValueToDefVecMap& valueToDefVecMap,
+ const TargetMachine& target) {
SchedGraphNode* node = getGraphNodeForInstr(&MI);
if (node == NULL)
return;
case MachineOperand::MO_UnextendedImmed:
case MachineOperand::MO_PCRelativeDisp:
case MachineOperand::MO_ConstantPoolIndex:
- break; // nothing to do for immediate fields
+ break; // nothing to do for immediate fields
default:
assert(0 && "Unknown machine operand type in SchedGraph builder");
void SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target,
- SchedGraphNode* node,
- std::vector<SchedGraphNode*>& memNodeVec,
- std::vector<SchedGraphNode*>& callDepNodeVec,
- RegToRefVecMap& regToRefVecMap,
- ValueToDefVecMap& valueToDefVecMap) {
+ SchedGraphNode* node,
+ std::vector<SchedGraphNode*>& memNodeVec,
+ std::vector<SchedGraphNode*>& callDepNodeVec,
+ RegToRefVecMap& regToRefVecMap,
+ ValueToDefVecMap& valueToDefVecMap) {
const TargetInstrInfo& mii = *target.getInstrInfo();
MachineOpCode opCode = node->getOpcode();
void SchedGraph::buildNodesForBB(const TargetMachine& target,
- MachineBasicBlock& MBB,
- std::vector<SchedGraphNode*>& memNodeVec,
- std::vector<SchedGraphNode*>& callDepNodeVec,
- RegToRefVecMap& regToRefVecMap,
- ValueToDefVecMap& valueToDefVecMap) {
+ MachineBasicBlock& MBB,
+ std::vector<SchedGraphNode*>& memNodeVec,
+ std::vector<SchedGraphNode*>& callDepNodeVec,
+ RegToRefVecMap& regToRefVecMap,
+ ValueToDefVecMap& valueToDefVecMap) {
const TargetInstrInfo& mii = *target.getInstrInfo();
// Build graph nodes for each VM instruction and gather def/use info.
this->addMachineRegEdges(regToRefVecMap, target);
// Finally, add edges from the dummy root and to dummy leaf
- this->addDummyEdges();
+ this->addDummyEdges();
}
// class SchedGraphSet
//
SchedGraphSet::SchedGraphSet(const Function* _function,
- const TargetMachine& target) :
+ const TargetMachine& target) :
function(_function) {
buildGraphsForMethod(function, target);
}
void SchedGraphSet::buildGraphsForMethod(const Function *F,
- const TargetMachine& target) {
+ const TargetMachine& target) {
MachineFunction &MF = MachineFunction::get(F);
for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
addGraph(new SchedGraph(*I, target));
<< sink->getNodeId() << "] : ";
switch(depType) {
- case SchedGraphEdge::CtrlDep:
+ case SchedGraphEdge::CtrlDep:
os<< "Control Dep";
break;
case SchedGraphEdge::ValueDep:
os<< "Reg Value " << *val;
break;
- case SchedGraphEdge::MemoryDep:
+ case SchedGraphEdge::MemoryDep:
os<< "Memory Dep";
break;
case SchedGraphEdge::MachineRegister:
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