Add new optional getPassName() virtual function that a Pass can override

[oota-llvm.git] / lib / Target / SparcV9 / InstrSched / InstrScheduling.cpp

diff --git a/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp b/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp
index 31eca3903b106c7375b2fbc66fb9f49f84e803bd..b0422797475193f48454333b4e5fb23dbe22d28e 100644 (file)
--- a/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp
+++ b/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp
@@ -1,20 +1,15 @@
-// $Id$
-//***************************************************************************
-// File:
-//     InstrScheduling.cpp
-// 
-// Purpose:
-//     
-// History:
-//     7/23/01  -  Vikram Adve  -  Created
-//**************************************************************************/
-
+//===- InstrScheduling.cpp - Generic Instruction Scheduling support -------===//
+//
+// This file implements the llvm/CodeGen/InstrScheduling.h interface, along with
+// generic support routines for instruction scheduling.
+//
+//===----------------------------------------------------------------------===//
 
 #include "llvm/CodeGen/InstrScheduling.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineCodeForInstruction.h"
 #include "llvm/CodeGen/MachineCodeForMethod.h"
-#include "llvm/Analysis/LiveVar/MethodLiveVarInfo.h" // FIXME: Remove when AnalysisUsage sets can be symbolic!
+#include "llvm/Analysis/LiveVar/FunctionLiveVarInfo.h" // FIXME: Remove when modularized better
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/BasicBlock.h"
 #include "llvm/Instruction.h"
@@ -364,10 +359,14 @@ private:
                                                // indexed by branch node ptr 
   
 public:
-  /*ctor*/     SchedulingManager       (const TargetMachine& _target,
-                                        const SchedGraph* graph,
-                                        SchedPriorities& schedPrio);
-  /*dtor*/     ~SchedulingManager      () {}
+  SchedulingManager(const TargetMachine& _target, const SchedGraph* graph,
+                    SchedPriorities& schedPrio);
+  ~SchedulingManager() {
+    for (std::hash_map<const SchedGraphNode*,
+           DelaySlotInfo*>::iterator I = delaySlotInfoForBranches.begin(),
+           E = delaySlotInfoForBranches.end(); I != E; ++I)
+      delete I->second;
+  }
   
   //----------------------------------------------------------------------
   // Simplify access to the machine instruction info
@@ -497,30 +496,21 @@ public:
   inline DelaySlotInfo* getDelaySlotInfoForInstr(const SchedGraphNode* bn,
                                                 bool createIfMissing=false)
   {
-    DelaySlotInfo* dinfo;
-    std::hash_map<const SchedGraphNode*, DelaySlotInfo* >::const_iterator
+    std::hash_map<const SchedGraphNode*, DelaySlotInfo*>::const_iterator
       I = delaySlotInfoForBranches.find(bn);
-    if (I == delaySlotInfoForBranches.end())
-      {
-       if (createIfMissing)
-         {
-           dinfo = new DelaySlotInfo(bn,
-                          getInstrInfo().getNumDelaySlots(bn->getOpCode()));
-           delaySlotInfoForBranches[bn] = dinfo;
-         }
-       else
-         dinfo = NULL;
-      }
-    else
-      dinfo = (*I).second;
-    
-    return dinfo;
+    if (I != delaySlotInfoForBranches.end())
+      return I->second;
+
+    if (!createIfMissing) return 0;
+
+    DelaySlotInfo *dinfo =
+      new DelaySlotInfo(bn, getInstrInfo().getNumDelaySlots(bn->getOpCode()));
+    return delaySlotInfoForBranches[bn] = dinfo;
   }
   
 private:
-  /*ctor*/     SchedulingManager       ();     // Disable: DO NOT IMPLEMENT.
-  void         updateEarliestStartTimes(const SchedGraphNode* node,
-                                        cycles_t schedTime);
+  SchedulingManager();     // DISABLED: DO NOT IMPLEMENT
+  void updateEarliestStartTimes(const SchedGraphNode* node, cycles_t schedTime);
 };
 
 
@@ -671,7 +661,6 @@ RecordSchedule(const BasicBlock* bb, const SchedulingManager& S)
   // Erase all except the dummy PHI instructions from mvec, and
   // pre-allocate create space for the ones we will put back in.
   mvec.erase(I, mvec.end());
-  mvec.reserve(mvec.size() + S.isched.getNumInstructions());
   
   InstrSchedule::const_iterator NIend = S.isched.end();
   for (InstrSchedule::const_iterator NI = S.isched.begin(); NI != NIend; ++NI)
@@ -1491,26 +1480,25 @@ instrIsFeasible(const SchedulingManager& S,
 //---------------------------------------------------------------------------
 
 namespace {
-  class InstructionSchedulingWithSSA : public MethodPass {
+  class InstructionSchedulingWithSSA : public FunctionPass {
     const TargetMachine &target;
   public:
     inline InstructionSchedulingWithSSA(const TargetMachine &T) : target(T) {}
+
+    const char *getPassName() const { return "Instruction Scheduling"; }
   
-    // getAnalysisUsageInfo - We use LiveVarInfo...
-    virtual void getAnalysisUsageInfo(Pass::AnalysisSet &Requires,
-                                      Pass::AnalysisSet &Destroyed,
-                                      Pass::AnalysisSet &Provided) {
-      Requires.push_back(MethodLiveVarInfo::ID);
-      Destroyed.push_back(MethodLiveVarInfo::ID);
+    // getAnalysisUsage - We use LiveVarInfo...
+    virtual void getAnalysisUsage(AnalysisUsage &AU) const {
+      AU.addRequired(FunctionLiveVarInfo::ID);
     }
     
-    bool runOnMethod(Method *M);
+    bool runOnFunction(Function *F);
   };
 } // end anonymous namespace
 
 
 bool
-InstructionSchedulingWithSSA::runOnMethod(Method *M)
+InstructionSchedulingWithSSA::runOnFunction(Function *M)
 {
   if (SchedDebugLevel == Sched_Disable)
     return false;
@@ -1535,7 +1523,7 @@ InstructionSchedulingWithSSA::runOnMethod(Method *M)
         cerr << "\n*** TRACE OF INSTRUCTION SCHEDULING OPERATIONS\n\n";
       
       // expensive!
-      SchedPriorities schedPrio(M, graph,getAnalysis<MethodLiveVarInfo>());
+      SchedPriorities schedPrio(M, graph,getAnalysis<FunctionLiveVarInfo>());
       SchedulingManager S(target, graph, schedPrio);
           
       ChooseInstructionsForDelaySlots(S, bb, graph); // modifies graph
@@ -1555,8 +1543,6 @@ InstructionSchedulingWithSSA::runOnMethod(Method *M)
 }
 
 
-MethodPass*
-createInstructionSchedulingWithSSAPass(const TargetMachine &tgt)
-{
+Pass *createInstructionSchedulingWithSSAPass(const TargetMachine &tgt) {
   return new InstructionSchedulingWithSSA(tgt);
 }