Merge my changes with brians

[oota-llvm.git] / lib / Target / SparcV8 / SparcV8RegisterInfo.td

diff --git a/lib/Target/SparcV8/SparcV8RegisterInfo.td b/lib/Target/SparcV8/SparcV8RegisterInfo.td
index d5167e2aebf2fa2bacc3f9b8757cf513bf3b3f18..ca0bcdc171cefac2efd118fe30cf7fcafee4624f 100644 (file)
--- a/lib/Target/SparcV8/SparcV8RegisterInfo.td
+++ b/lib/Target/SparcV8/SparcV8RegisterInfo.td
@@ -24,6 +24,11 @@ class Rf<bits<5> num> : Register {
 class Rd<bits<5> num> : Register {
   field bits<5> Num = num;
 }
+// Rs - Special "ancillary state registers" registers, like the Y, ASR, PSR,
+// WIM, TBR, etc registers
+class Rs<bits<5> num> : Register {
+  field bits<5> Num = num;
+}
 
 let Namespace = "V8" in {
   def G0 : Ri< 0>;    def G1 : Ri< 1>;    def G2 : Ri< 2>;    def G3 : Ri< 3>;
@@ -53,6 +58,9 @@ let Namespace = "V8" in {
   def D4  : Rd< 8>; def D5  : Rd<10>; def D6  : Rd<12>; def D7  : Rd<14>;
   def D8  : Rd<16>; def D9  : Rd<18>; def D10 : Rd<20>; def D11 : Rd<22>;
   def D12 : Rd<24>; def D13 : Rd<26>; def D14 : Rd<28>; def D15 : Rd<30>;
+
+  // The Y register.
+  def Y   : Rs<0>;
 }
 
 
@@ -61,10 +69,18 @@ let Namespace = "V8" in {
 // FIXME: the register order should be defined in terms of the preferred
 // allocation order...
 //
-def IntRegs : RegisterClass<i32, 8, [G1, G2, G3, G4, G5, G6, G7, G0,
-                                     O0, O1, O2, O3, O4, O5, O6, O7,
+def IntRegs : RegisterClass<i32, 8, [G1, G2, G3, G4, G5, G6, G7,
+                                     O0, O1, O2, O3, O4, O5, O7,
                                      L0, L1, L2, L3, L4, L5, L6, L7,
-                                     I0, I1, I2, I3, I4, I5, I6, I7]>;
+                                     I0, I1, I2, I3, I4, I5,
+                                     // Non-allocatable regs
+                                     O6, I6, I7, G0]> {
+  let Methods = [{
+    iterator allocation_order_end(MachineFunction &MF) const {
+      return end()-4;  // Don't allocate special registers
+    }
+  }];
+}
 
 def FPRegs : RegisterClass<f32, 4, [F0, F1, F2, F3, F4, F5, F6, F7, F8,
   F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21, F22,