Merge my changes with brians

[oota-llvm.git] / lib / Target / SparcV8 / SparcV8RegisterInfo.td

diff --git a/lib/Target/SparcV8/SparcV8RegisterInfo.td b/lib/Target/SparcV8/SparcV8RegisterInfo.td
index 09246c0a41e7a481ba563460f99921751e5b7e45..ca0bcdc171cefac2efd118fe30cf7fcafee4624f 100644 (file)
--- a/lib/Target/SparcV8/SparcV8RegisterInfo.td
+++ b/lib/Target/SparcV8/SparcV8RegisterInfo.td
@@ -24,6 +24,11 @@ class Rf<bits<5> num> : Register {
 class Rd<bits<5> num> : Register {
   field bits<5> Num = num;
 }
+// Rs - Special "ancillary state registers" registers, like the Y, ASR, PSR,
+// WIM, TBR, etc registers
+class Rs<bits<5> num> : Register {
+  field bits<5> Num = num;
+}
 
 let Namespace = "V8" in {
   def G0 : Ri< 0>;    def G1 : Ri< 1>;    def G2 : Ri< 2>;    def G3 : Ri< 3>;
@@ -53,6 +58,9 @@ let Namespace = "V8" in {
   def D4  : Rd< 8>; def D5  : Rd<10>; def D6  : Rd<12>; def D7  : Rd<14>;
   def D8  : Rd<16>; def D9  : Rd<18>; def D10 : Rd<20>; def D11 : Rd<22>;
   def D12 : Rd<24>; def D13 : Rd<26>; def D14 : Rd<28>; def D15 : Rd<30>;
+
+  // The Y register.
+  def Y   : Rs<0>;
 }