AMDGPU/SI: Add SI Machine Scheduler

[oota-llvm.git] / lib / Target / Sparc / SparcRegisterInfo.h

diff --git a/lib/Target/Sparc/SparcRegisterInfo.h b/lib/Target/Sparc/SparcRegisterInfo.h
index 1481f5fb1a8b68768860780da5beae70cad57ec3..32075b1df410bc2feafb8b8798b7b6de11025035 100644 (file)
--- a/lib/Target/Sparc/SparcRegisterInfo.h
+++ b/lib/Target/Sparc/SparcRegisterInfo.h
@@ -1,55 +1,51 @@
-//===- SparcV8RegisterInfo.h - SparcV8 Register Information Impl -*- C++ -*-==//
-// 
+//===-- SparcRegisterInfo.h - Sparc Register Information Impl ---*- C++ -*-===//
+//
 //                     The LLVM Compiler Infrastructure
 //
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
 //===----------------------------------------------------------------------===//
 //
-// This file contains the SparcV8 implementation of the MRegisterInfo class.
+// This file contains the Sparc implementation of the TargetRegisterInfo class.
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef SPARCV8REGISTERINFO_H
-#define SPARCV8REGISTERINFO_H
+#ifndef LLVM_LIB_TARGET_SPARC_SPARCREGISTERINFO_H
+#define LLVM_LIB_TARGET_SPARC_SPARCREGISTERINFO_H
+
+#include "llvm/Target/TargetRegisterInfo.h"
 
-#include "llvm/Target/MRegisterInfo.h"
-#include "SparcV8GenRegisterInfo.h.inc"
+#define GET_REGINFO_HEADER
+#include "SparcGenRegisterInfo.inc"
 
 namespace llvm {
+struct SparcRegisterInfo : public SparcGenRegisterInfo {
+  SparcRegisterInfo();
 
-class Type;
+  /// Code Generation virtual methods...
+  const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
+  const uint32_t *getCallPreservedMask(const MachineFunction &MF,
+                                       CallingConv::ID CC) const override;
 
-struct SparcV8RegisterInfo : public SparcV8GenRegisterInfo {
-  SparcV8RegisterInfo();
-  const TargetRegisterClass* getRegClassForType(const Type* Ty) const;
+  const uint32_t* getRTCallPreservedMask(CallingConv::ID CC) const;
+
+  BitVector getReservedRegs(const MachineFunction &MF) const override;
+
+  const TargetRegisterClass *getPointerRegClass(const MachineFunction &MF,
+                                                unsigned Kind) const override;
+
+  void eliminateFrameIndex(MachineBasicBlock::iterator II,
+                           int SPAdj, unsigned FIOperandNum,
+                           RegScavenger *RS = nullptr) const override;
+
+  void processFunctionBeforeFrameFinalized(MachineFunction &MF,
+                                       RegScavenger *RS = nullptr) const;
+
+  unsigned getFrameRegister(const MachineFunction &MF) const override;
+
+  bool canRealignStack(const MachineFunction &MF) const override;
 
-  /// Code Generation virtual methods...
-  int storeRegToStackSlot(MachineBasicBlock &MBB,
-                          MachineBasicBlock::iterator MBBI,
-                          unsigned SrcReg, int FrameIndex,
-                          const TargetRegisterClass *RC) const;
-
-  int loadRegFromStackSlot(MachineBasicBlock &MBB,
-                           MachineBasicBlock::iterator MBBI,
-                           unsigned DestReg, int FrameIndex,
-                           const TargetRegisterClass *RC) const;
-  
-  int copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
-                  unsigned DestReg, unsigned SrcReg,
-                  const TargetRegisterClass *RC) const;
-
-  void eliminateCallFramePseudoInstr(MachineFunction &MF,
-                                     MachineBasicBlock &MBB,
-                                     MachineBasicBlock::iterator I) const;
-
-  void eliminateFrameIndex(MachineBasicBlock::iterator II) const;
-
-  void processFunctionBeforeFrameFinalized(MachineFunction &MF) const;
-
-  void emitPrologue(MachineFunction &MF) const;
-  void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
 };
 
 } // end namespace llvm