-//===- SparcV8RegisterInfo.cpp - SparcV8 Register Information ---*- C++ -*-===//
+//===-- SparcRegisterInfo.cpp - SPARC Register Information ----------------===//
//
// The LLVM Compiler Infrastructure
//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
-// This file contains the SparcV8 implementation of the MRegisterInfo class.
+// This file contains the SPARC implementation of the TargetRegisterInfo class.
//
//===----------------------------------------------------------------------===//
-#include "SparcV8.h"
-#include "SparcV8RegisterInfo.h"
-#include "llvm/CodeGen/MachineInstrBuilder.h"
-#include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/CodeGen/MachineFrameInfo.h"
-#include "llvm/Type.h"
+#include "SparcRegisterInfo.h"
+#include "Sparc.h"
+#include "SparcMachineFunctionInfo.h"
+#include "SparcSubtarget.h"
+#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/STLExtras.h"
-#include <iostream>
+#include "llvm/CodeGen/MachineFrameInfo.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/IR/Type.h"
+#include "llvm/Support/CommandLine.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Target/TargetInstrInfo.h"
+
+#define GET_REGINFO_TARGET_DESC
+#include "SparcGenRegisterInfo.inc"
+
using namespace llvm;
-SparcV8RegisterInfo::SparcV8RegisterInfo()
- : SparcV8GenRegisterInfo(V8::ADJCALLSTACKDOWN,
- V8::ADJCALLSTACKUP) {}
-
-static const TargetRegisterClass *getClass(unsigned SrcReg) {
- if (V8::IntRegsRegisterClass->contains(SrcReg))
- return V8::IntRegsRegisterClass;
- else if (V8::FPRegsRegisterClass->contains(SrcReg))
- return V8::FPRegsRegisterClass;
- else if (V8::DFPRegsRegisterClass->contains(SrcReg))
- return V8::DFPRegsRegisterClass;
- else {
- std::cerr << "Error: register of unknown class found: " << SrcReg << "\n";
- abort ();
- }
+static cl::opt<bool>
+ReserveAppRegisters("sparc-reserve-app-registers", cl::Hidden, cl::init(false),
+ cl::desc("Reserve application registers (%g2-%g4)"));
+
+SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st)
+ : SparcGenRegisterInfo(SP::O7), Subtarget(st) {
}
-void SparcV8RegisterInfo::
-storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
- unsigned SrcReg, int FrameIdx,
- const TargetRegisterClass *rc) const {
- const TargetRegisterClass *RC = getClass(SrcReg);
-
- // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
- if (RC == V8::IntRegsRegisterClass)
- BuildMI (MBB, I, V8::ST, 3).addFrameIndex (FrameIdx).addSImm (0)
- .addReg (SrcReg);
- else if (RC == V8::FPRegsRegisterClass)
- BuildMI (MBB, I, V8::STFri, 3).addFrameIndex (FrameIdx).addSImm (0)
- .addReg (SrcReg);
- else if (RC == V8::DFPRegsRegisterClass)
- BuildMI (MBB, I, V8::STDFri, 3).addFrameIndex (FrameIdx).addSImm (0)
- .addReg (SrcReg);
- else
- assert (0 && "Can't store this register to stack slot");
+const uint16_t* SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
+ const {
+ return CSR_SaveList;
}
-void SparcV8RegisterInfo::
-loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
- unsigned DestReg, int FrameIdx,
- const TargetRegisterClass *rc) const {
- const TargetRegisterClass *RC = getClass(DestReg);
- if (RC == V8::IntRegsRegisterClass)
- BuildMI (MBB, I, V8::LD, 2, DestReg).addFrameIndex (FrameIdx).addSImm (0);
- else if (RC == V8::FPRegsRegisterClass)
- BuildMI (MBB, I, V8::LDFri, 2, DestReg).addFrameIndex (FrameIdx)
- .addSImm (0);
- else if (RC == V8::DFPRegsRegisterClass)
- BuildMI (MBB, I, V8::LDDFri, 2, DestReg).addFrameIndex (FrameIdx)
- .addSImm (0);
- else
- assert(0 && "Can't load this register from stack slot");
+const uint32_t*
+SparcRegisterInfo::getCallPreservedMask(CallingConv::ID CC) const {
+ return CSR_RegMask;
}
-void SparcV8RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator I,
- unsigned DestReg, unsigned SrcReg,
- const TargetRegisterClass *RC) const {
- if (RC == V8::IntRegsRegisterClass)
- BuildMI (MBB, I, V8::ORrr, 2, DestReg).addReg (V8::G0).addReg (SrcReg);
- else if (RC == V8::FPRegsRegisterClass)
- BuildMI (MBB, I, V8::FMOVS, 1, DestReg).addReg (SrcReg);
- else if (RC == V8::DFPRegsRegisterClass)
- BuildMI (MBB, I, V8::FpMOVD, 1, DestReg).addReg (SrcReg);
- else
- assert (0 && "Can't copy this register");
+const uint32_t*
+SparcRegisterInfo::getRTCallPreservedMask(CallingConv::ID CC) const {
+ return RTCSR_RegMask;
}
-void SparcV8RegisterInfo::
-eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
- MachineBasicBlock::iterator I) const {
- MachineInstr &MI = *I;
- int size = MI.getOperand (0).getImmedValue ();
- if (MI.getOpcode () == V8::ADJCALLSTACKDOWN)
- size = -size;
- BuildMI (MBB, I, V8::ADDri, 2, V8::SP).addReg (V8::SP).addSImm (size);
- MBB.erase (I);
+BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
+ BitVector Reserved(getNumRegs());
+ // FIXME: G1 reserved for now for large imm generation by frame code.
+ Reserved.set(SP::G1);
+
+ // G1-G4 can be used in applications.
+ if (ReserveAppRegisters) {
+ Reserved.set(SP::G2);
+ Reserved.set(SP::G3);
+ Reserved.set(SP::G4);
+ }
+ // G5 is not reserved in 64 bit mode.
+ if (!Subtarget.is64Bit())
+ Reserved.set(SP::G5);
+
+ Reserved.set(SP::O6);
+ Reserved.set(SP::I6);
+ Reserved.set(SP::I7);
+ Reserved.set(SP::G0);
+ Reserved.set(SP::G6);
+ Reserved.set(SP::G7);
+
+ // Unaliased double registers are not available in non-V9 targets.
+ if (!Subtarget.isV9()) {
+ for (unsigned n = 0; n != 16; ++n) {
+ for (MCRegAliasIterator AI(SP::D16 + n, this, true); AI.isValid(); ++AI)
+ Reserved.set(*AI);
+ }
+ }
+
+ return Reserved;
}
-void
-SparcV8RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
- unsigned i = 0;
- MachineInstr &MI = *II;
- while (!MI.getOperand(i).isFrameIndex()) {
- ++i;
- assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
+const TargetRegisterClass*
+SparcRegisterInfo::getPointerRegClass(const MachineFunction &MF,
+ unsigned Kind) const {
+ return Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass;
+}
+
+static void replaceFI(MachineFunction &MF,
+ MachineBasicBlock::iterator II,
+ MachineInstr &MI,
+ DebugLoc dl,
+ unsigned FIOperandNum, int Offset,
+ unsigned FramePtr)
+{
+ // Replace frame index with a frame pointer reference.
+ if (Offset >= -4096 && Offset <= 4095) {
+ // If the offset is small enough to fit in the immediate field, directly
+ // encode it.
+ MI.getOperand(FIOperandNum).ChangeToRegister(FramePtr, false);
+ MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
+ return;
}
- int FrameIndex = MI.getOperand(i).getFrameIndex();
+ const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
+
+ // FIXME: it would be better to scavenge a register here instead of
+ // reserving G1 all of the time.
+ if (Offset >= 0) {
+ // Emit nonnegaive immediates with sethi + or.
+ // sethi %hi(Offset), %g1
+ // add %g1, %fp, %g1
+ // Insert G1+%lo(offset) into the user.
+ BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1)
+ .addImm(HI22(Offset));
+
+
+ // Emit G1 = G1 + I6
+ BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
+ .addReg(FramePtr);
+ // Insert: G1+%lo(offset) into the user.
+ MI.getOperand(FIOperandNum).ChangeToRegister(SP::G1, false);
+ MI.getOperand(FIOperandNum + 1).ChangeToImmediate(LO10(Offset));
+ return;
+ }
+
+ // Emit Negative numbers with sethi + xor
+ // sethi %hix(Offset), %g1
+ // xor %g1, %lox(offset), %g1
+ // add %g1, %fp, %g1
+ // Insert: G1 + 0 into the user.
+ BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1)
+ .addImm(HIX22(Offset));
+ BuildMI(*MI.getParent(), II, dl, TII.get(SP::XORri), SP::G1)
+ .addReg(SP::G1).addImm(LOX10(Offset));
+
+ BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
+ .addReg(FramePtr);
+ // Insert: G1+%lo(offset) into the user.
+ MI.getOperand(FIOperandNum).ChangeToRegister(SP::G1, false);
+ MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0);
+}
- // Replace frame index with a frame pointer reference
- MI.SetMachineOperandReg (i, V8::FP);
+
+void
+SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
+ int SPAdj, unsigned FIOperandNum,
+ RegScavenger *RS) const {
+ assert(SPAdj == 0 && "Unexpected");
+
+ MachineInstr &MI = *II;
+ DebugLoc dl = MI.getDebugLoc();
+ int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
// Addressable stack objects are accessed using neg. offsets from %fp
MachineFunction &MF = *MI.getParent()->getParent();
- int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
- MI.getOperand(i+1).getImmedValue();
- // note: Offset < 0
- MI.SetMachineOperandConst (i+1, MachineOperand::MO_SignExtendedImmed, Offset);
-}
+ int64_t Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
+ MI.getOperand(FIOperandNum + 1).getImm() +
+ Subtarget.getStackPointerBias();
+ SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
+ unsigned FramePtr = SP::I6;
+ if (FuncInfo->isLeafProc()) {
+ // Use %sp and adjust offset if needed.
+ FramePtr = SP::O6;
+ int stackSize = MF.getFrameInfo()->getStackSize();
+ Offset += (stackSize) ? Subtarget.getAdjustedFrameSize(stackSize) : 0 ;
+ }
-void SparcV8RegisterInfo::
-processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
-
-void SparcV8RegisterInfo::emitPrologue(MachineFunction &MF) const {
- MachineBasicBlock &MBB = MF.front();
- MachineFrameInfo *MFI = MF.getFrameInfo();
-
- // Get the number of bytes to allocate from the FrameInfo
- int NumBytes = (int) MFI->getStackSize();
-
- // Emit the correct save instruction based on the number of bytes in
- // the frame. Minimum stack frame size according to V8 ABI is:
- // 16 words for register window spill
- // 1 word for address of returned aggregate-value
- // + 6 words for passing parameters on the stack
- // ----------
- // 23 words * 4 bytes per word = 92 bytes
- NumBytes += 92;
- // Round up to next doubleword boundary -- a double-word boundary
- // is required by the ABI.
- NumBytes = (NumBytes + 7) & ~7;
- BuildMI(MBB, MBB.begin(), V8::SAVEri, 2,
- V8::SP).addImm(-NumBytes).addReg(V8::SP);
-}
+ if (!Subtarget.isV9() || !Subtarget.hasHardQuad()) {
+ if (MI.getOpcode() == SP::STQFri) {
+ const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
+ unsigned SrcReg = MI.getOperand(2).getReg();
+ unsigned SrcEvenReg = getSubReg(SrcReg, SP::sub_even64);
+ unsigned SrcOddReg = getSubReg(SrcReg, SP::sub_odd64);
+ MachineInstr *StMI =
+ BuildMI(*MI.getParent(), II, dl, TII.get(SP::STDFri))
+ .addReg(FramePtr).addImm(0).addReg(SrcEvenReg);
+ replaceFI(MF, II, *StMI, dl, 0, Offset, FramePtr);
+ MI.setDesc(TII.get(SP::STDFri));
+ MI.getOperand(2).setReg(SrcOddReg);
+ Offset += 8;
+ } else if (MI.getOpcode() == SP::LDQFri) {
+ const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
+ unsigned DestReg = MI.getOperand(0).getReg();
+ unsigned DestEvenReg = getSubReg(DestReg, SP::sub_even64);
+ unsigned DestOddReg = getSubReg(DestReg, SP::sub_odd64);
+ MachineInstr *StMI =
+ BuildMI(*MI.getParent(), II, dl, TII.get(SP::LDDFri), DestEvenReg)
+ .addReg(FramePtr).addImm(0);
+ replaceFI(MF, II, *StMI, dl, 1, Offset, FramePtr);
+
+ MI.setDesc(TII.get(SP::LDDFri));
+ MI.getOperand(0).setReg(DestOddReg);
+ Offset += 8;
+ }
+ }
-void SparcV8RegisterInfo::emitEpilogue(MachineFunction &MF,
- MachineBasicBlock &MBB) const {
- MachineBasicBlock::iterator MBBI = prior(MBB.end());
- assert(MBBI->getOpcode() == V8::RETL &&
- "Can only put epilog before 'retl' instruction!");
- BuildMI(MBB, MBBI, V8::RESTORErr, 2, V8::G0).addReg(V8::G0).addReg(V8::G0);
-}
+ replaceFI(MF, II, MI, dl, FIOperandNum, Offset, FramePtr);
-#include "SparcV8GenRegisterInfo.inc"
+}
-const TargetRegisterClass*
-SparcV8RegisterInfo::getRegClassForType(const Type* Ty) const {
- switch (Ty->getTypeID()) {
- case Type::FloatTyID: return V8::FPRegsRegisterClass;
- case Type::DoubleTyID: return V8::DFPRegsRegisterClass;
- case Type::LongTyID:
- case Type::ULongTyID: assert(0 && "Long values do not fit in registers!");
- default: assert(0 && "Invalid type to getClass!");
- case Type::BoolTyID:
- case Type::SByteTyID:
- case Type::UByteTyID:
- case Type::ShortTyID:
- case Type::UShortTyID:
- case Type::IntTyID:
- case Type::UIntTyID:
- case Type::PointerTyID: return V8::IntRegsRegisterClass;
- }
+unsigned SparcRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
+ return SP::I6;
}
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