#include "SparcSubtarget.h"
#include "Sparc.h"
#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/Support/ErrorHandling.h"
#include "SparcGenInstrInfo.inc"
using namespace llvm;
}
static bool isZeroImm(const MachineOperand &op) {
- return op.isImmediate() && op.getImm() == 0;
+ return op.isImm() && op.getImm() == 0;
}
/// Return true if the instruction is a register to register move and
/// leave the source and dest operands in the passed parameters.
///
bool SparcInstrInfo::isMoveInstr(const MachineInstr &MI,
- unsigned &SrcReg, unsigned &DstReg) const {
+ unsigned &SrcReg, unsigned &DstReg,
+ unsigned &SrcSR, unsigned &DstSR) const {
+ SrcSR = DstSR = 0; // No sub-registers.
+
// We look for 3 kinds of patterns here:
// or with G0 or 0
// add with G0 or 0
return true;
}
} else if ((MI.getOpcode() == SP::ORri || MI.getOpcode() == SP::ADDri) &&
- isZeroImm(MI.getOperand(2)) && MI.getOperand(1).isRegister()) {
+ isZeroImm(MI.getOperand(2)) && MI.getOperand(1).isReg()) {
DstReg = MI.getOperand(0).getReg();
SrcReg = MI.getOperand(1).getReg();
return true;
/// the destination along with the FrameIndex of the loaded stack slot. If
/// not, return 0. This predicate must return 0 if the instruction has
/// any side effects other than loading from the stack slot.
-unsigned SparcInstrInfo::isLoadFromStackSlot(MachineInstr *MI,
+unsigned SparcInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
int &FrameIndex) const {
if (MI->getOpcode() == SP::LDri ||
MI->getOpcode() == SP::LDFri ||
MI->getOpcode() == SP::LDDFri) {
- if (MI->getOperand(1).isFrameIndex() && MI->getOperand(2).isImmediate() &&
+ if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() &&
MI->getOperand(2).getImm() == 0) {
FrameIndex = MI->getOperand(1).getIndex();
return MI->getOperand(0).getReg();
/// the source reg along with the FrameIndex of the loaded stack slot. If
/// not, return 0. This predicate must return 0 if the instruction has
/// any side effects other than storing to the stack slot.
-unsigned SparcInstrInfo::isStoreToStackSlot(MachineInstr *MI,
+unsigned SparcInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
int &FrameIndex) const {
if (MI->getOpcode() == SP::STri ||
MI->getOpcode() == SP::STFri ||
MI->getOpcode() == SP::STDFri) {
- if (MI->getOperand(0).isFrameIndex() && MI->getOperand(1).isImmediate() &&
+ if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() &&
MI->getOperand(1).getImm() == 0) {
FrameIndex = MI->getOperand(0).getIndex();
return MI->getOperand(2).getReg();
SparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond)const{
+ // FIXME this should probably take a DebugLoc argument
+ DebugLoc dl = DebugLoc::getUnknownLoc();
// Can only insert uncond branches so far.
assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!");
- BuildMI(&MBB, get(SP::BA)).addMBB(TBB);
+ BuildMI(&MBB, dl, get(SP::BA)).addMBB(TBB);
return 1;
}
bool SparcInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator I,
- unsigned DestReg, unsigned SrcReg,
- const TargetRegisterClass *DestRC,
- const TargetRegisterClass *SrcRC) const {
+ MachineBasicBlock::iterator I,
+ unsigned DestReg, unsigned SrcReg,
+ const TargetRegisterClass *DestRC,
+ const TargetRegisterClass *SrcRC) const {
if (DestRC != SrcRC) {
// Not yet supported!
return false;
}
+ DebugLoc DL = DebugLoc::getUnknownLoc();
+ if (I != MBB.end()) DL = I->getDebugLoc();
+
if (DestRC == SP::IntRegsRegisterClass)
- BuildMI(MBB, I, get(SP::ORrr), DestReg).addReg(SP::G0).addReg(SrcReg);
+ BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0).addReg(SrcReg);
else if (DestRC == SP::FPRegsRegisterClass)
- BuildMI(MBB, I, get(SP::FMOVS), DestReg).addReg(SrcReg);
+ BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg).addReg(SrcReg);
else if (DestRC == SP::DFPRegsRegisterClass)
- BuildMI(MBB, I, get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD),DestReg)
+ BuildMI(MBB, I, DL, get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD),DestReg)
.addReg(SrcReg);
else
// Can't copy this register
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned SrcReg, bool isKill, int FI,
const TargetRegisterClass *RC) const {
+ DebugLoc DL = DebugLoc::getUnknownLoc();
+ if (I != MBB.end()) DL = I->getDebugLoc();
+
// On the order of operands here: think "[FrameIdx + 0] = SrcReg".
if (RC == SP::IntRegsRegisterClass)
- BuildMI(MBB, I, get(SP::STri)).addFrameIndex(FI).addImm(0)
- .addReg(SrcReg, false, false, isKill);
+ BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0)
+ .addReg(SrcReg, getKillRegState(isKill));
else if (RC == SP::FPRegsRegisterClass)
- BuildMI(MBB, I, get(SP::STFri)).addFrameIndex(FI).addImm(0)
- .addReg(SrcReg, false, false, isKill);
+ BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0)
+ .addReg(SrcReg, getKillRegState(isKill));
else if (RC == SP::DFPRegsRegisterClass)
- BuildMI(MBB, I, get(SP::STDFri)).addFrameIndex(FI).addImm(0)
- .addReg(SrcReg, false, false, isKill);
+ BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0)
+ .addReg(SrcReg, getKillRegState(isKill));
else
- assert(0 && "Can't store this register to stack slot");
+ llvm_unreachable("Can't store this register to stack slot");
}
void SparcInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
- bool isKill,
- SmallVectorImpl<MachineOperand> &Addr,
- const TargetRegisterClass *RC,
+ bool isKill,
+ SmallVectorImpl<MachineOperand> &Addr,
+ const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const {
unsigned Opc = 0;
+ DebugLoc DL = DebugLoc::getUnknownLoc();
if (RC == SP::IntRegsRegisterClass)
Opc = SP::STri;
else if (RC == SP::FPRegsRegisterClass)
else if (RC == SP::DFPRegsRegisterClass)
Opc = SP::STDFri;
else
- assert(0 && "Can't load this register");
- MachineInstrBuilder MIB = BuildMI(MF, get(Opc));
- for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
- MachineOperand &MO = Addr[i];
- if (MO.isRegister())
- MIB.addReg(MO.getReg());
- else if (MO.isImmediate())
- MIB.addImm(MO.getImm());
- else {
- assert(MO.isFrameIndex());
- MIB.addFrameIndex(MO.getIndex());
- }
- }
- MIB.addReg(SrcReg, false, false, isKill);
+ llvm_unreachable("Can't load this register");
+ MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
+ for (unsigned i = 0, e = Addr.size(); i != e; ++i)
+ MIB.addOperand(Addr[i]);
+ MIB.addReg(SrcReg, getKillRegState(isKill));
NewMIs.push_back(MIB);
return;
}
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned DestReg, int FI,
const TargetRegisterClass *RC) const {
+ DebugLoc DL = DebugLoc::getUnknownLoc();
+ if (I != MBB.end()) DL = I->getDebugLoc();
+
if (RC == SP::IntRegsRegisterClass)
- BuildMI(MBB, I, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0);
+ BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0);
else if (RC == SP::FPRegsRegisterClass)
- BuildMI(MBB, I, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0);
+ BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0);
else if (RC == SP::DFPRegsRegisterClass)
- BuildMI(MBB, I, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0);
+ BuildMI(MBB, I, DL, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0);
else
- assert(0 && "Can't load this register from stack slot");
+ llvm_unreachable("Can't load this register from stack slot");
}
void SparcInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
- SmallVectorImpl<MachineOperand> &Addr,
- const TargetRegisterClass *RC,
+ SmallVectorImpl<MachineOperand> &Addr,
+ const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const {
unsigned Opc = 0;
if (RC == SP::IntRegsRegisterClass)
else if (RC == SP::DFPRegsRegisterClass)
Opc = SP::LDDFri;
else
- assert(0 && "Can't load this register");
- MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
- for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
- MachineOperand &MO = Addr[i];
- if (MO.isRegister())
- MIB.addReg(MO.getReg());
- else if (MO.isImmediate())
- MIB.addImm(MO.getImm());
- else {
- assert(MO.isFrameIndex());
- MIB.addFrameIndex(MO.getIndex());
- }
- }
+ llvm_unreachable("Can't load this register");
+ DebugLoc DL = DebugLoc::getUnknownLoc();
+ MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
+ for (unsigned i = 0, e = Addr.size(); i != e; ++i)
+ MIB.addOperand(Addr[i]);
NewMIs.push_back(MIB);
return;
}
-MachineInstr *SparcInstrInfo::foldMemoryOperand(MachineFunction &MF,
- MachineInstr* MI,
- SmallVectorImpl<unsigned> &Ops,
- int FI) const {
+MachineInstr *SparcInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
+ MachineInstr* MI,
+ const SmallVectorImpl<unsigned> &Ops,
+ int FI) const {
if (Ops.size() != 1) return NULL;
unsigned OpNum = Ops[0];
MachineInstr *NewMI = NULL;
switch (MI->getOpcode()) {
case SP::ORrr:
- if (MI->getOperand(1).isRegister() && MI->getOperand(1).getReg() == SP::G0&&
- MI->getOperand(0).isRegister() && MI->getOperand(2).isRegister()) {
+ if (MI->getOperand(1).isReg() && MI->getOperand(1).getReg() == SP::G0&&
+ MI->getOperand(0).isReg() && MI->getOperand(2).isReg()) {
if (OpNum == 0) // COPY -> STORE
- NewMI = BuildMI(MF, get(SP::STri)).addFrameIndex(FI).addImm(0)
- .addReg(MI->getOperand(2).getReg());
+ NewMI = BuildMI(MF, MI->getDebugLoc(), get(SP::STri))
+ .addFrameIndex(FI)
+ .addImm(0)
+ .addReg(MI->getOperand(2).getReg());
else // COPY -> LOAD
- NewMI = BuildMI(MF, get(SP::LDri), MI->getOperand(0).getReg())
- .addFrameIndex(FI).addImm(0);
+ NewMI = BuildMI(MF, MI->getDebugLoc(), get(SP::LDri),
+ MI->getOperand(0).getReg())
+ .addFrameIndex(FI)
+ .addImm(0);
}
break;
case SP::FMOVS:
if (OpNum == 0) { // COPY -> STORE
unsigned SrcReg = MI->getOperand(1).getReg();
bool isKill = MI->getOperand(1).isKill();
- NewMI = BuildMI(MF, get(isFloat ? SP::STFri : SP::STDFri))
- .addFrameIndex(FI).addImm(0).addReg(SrcReg, false, false, isKill);
+ bool isUndef = MI->getOperand(1).isUndef();
+ NewMI = BuildMI(MF, MI->getDebugLoc(),
+ get(isFloat ? SP::STFri : SP::STDFri))
+ .addFrameIndex(FI)
+ .addImm(0)
+ .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef));
} else { // COPY -> LOAD
unsigned DstReg = MI->getOperand(0).getReg();
bool isDead = MI->getOperand(0).isDead();
- NewMI = BuildMI(MF, get(isFloat ? SP::LDFri : SP::LDDFri))
- .addReg(DstReg, true, false, false, isDead).addFrameIndex(FI).addImm(0);
+ bool isUndef = MI->getOperand(0).isUndef();
+ NewMI = BuildMI(MF, MI->getDebugLoc(),
+ get(isFloat ? SP::LDFri : SP::LDDFri))
+ .addReg(DstReg, RegState::Define |
+ getDeadRegState(isDead) | getUndefRegState(isUndef))
+ .addFrameIndex(FI)
+ .addImm(0);
}
break;
}
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