-//===- SparcV8InstrFormats.td - SparcV8 Instr Formats ------*- tablegen -*-===//
-//
+//===-- SparcInstrFormats.td - Sparc Instruction Formats ---*- tablegen -*-===//
+//
// The LLVM Compiler Infrastructure
//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
//===----------------------------------------------------------------------===//
-class InstV8<dag ops, string asmstr, list<dag> pattern> : Instruction {
+class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction {
field bits<32> Inst;
- let Namespace = "V8";
+ let Namespace = "SP";
bits<2> op;
let Inst{31-30} = op; // Top two bits are the 'op' field
- dag OperandList = ops;
+ dag OutOperandList = outs;
+ dag InOperandList = ins;
let AsmString = asmstr;
let Pattern = pattern;
}
//===----------------------------------------------------------------------===//
-// Format #2 instruction classes in the SparcV8
+// Format #2 instruction classes in the Sparc
//===----------------------------------------------------------------------===//
// Format 2 instructions
-class F2<dag ops, string asmstr, list<dag> pattern>
- : InstV8<ops, asmstr, pattern> {
+class F2<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstSP<outs, ins, asmstr, pattern> {
bits<3> op2;
bits<22> imm22;
let op = 0; // op = 0
// Specific F2 classes: SparcV8 manual, page 44
//
-class F2_1<bits<3> op2Val, dag ops, string asmstr, list<dag> pattern>
- : F2<ops, asmstr, pattern> {
+class F2_1<bits<3> op2Val, dag outs, dag ins, string asmstr, list<dag> pattern>
+ : F2<outs, ins, asmstr, pattern> {
bits<5> rd;
let op2 = op2Val;
let Inst{29-25} = rd;
}
-class F2_2<bits<4> condVal, bits<3> op2Val, dag ops, string asmstr,
- list<dag> pattern> : F2<ops, asmstr, pattern> {
+class F2_2<bits<4> condVal, bits<3> op2Val, dag outs, dag ins, string asmstr,
+ list<dag> pattern> : F2<outs, ins, asmstr, pattern> {
bits<4> cond;
bit annul = 0; // currently unused
}
//===----------------------------------------------------------------------===//
-// Format #3 instruction classes in the SparcV8
+// Format #3 instruction classes in the Sparc
//===----------------------------------------------------------------------===//
-class F3<dag ops, string asmstr, list<dag> pattern>
- : InstV8<ops, asmstr, pattern> {
+class F3<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstSP<outs, ins, asmstr, pattern> {
bits<5> rd;
bits<6> op3;
bits<5> rs1;
// Specific F3 classes: SparcV8 manual, page 44
//
-class F3_1<bits<2> opVal, bits<6> op3val, dag ops,
- string asmstr, list<dag> pattern> : F3<ops, asmstr, pattern> {
- bits<8> asi = 0; // asi not currently used in SparcV8
+class F3_1<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
+ string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
+ bits<8> asi = 0; // asi not currently used
bits<5> rs2;
let op = opVal;
let Inst{4-0} = rs2;
}
-class F3_2<bits<2> opVal, bits<6> op3val, dag ops,
- string asmstr, list<dag> pattern> : F3<ops, asmstr, pattern> {
+class F3_2<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
+ string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
bits<13> simm13;
let op = opVal;
}
// floating-point
-class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag ops,
- string asmstr, list<dag> pattern> : F3<ops, asmstr, pattern> {
+class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
+ string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
bits<5> rs2;
let op = opVal;
let Inst{13-5} = opfval; // fp opcode
let Inst{4-0} = rs2;
}
+
+