-//===- SparcV8.td - Describe the SparcV8 Target Machine ---------*- C++ -*-===//
-//
+//===-- Sparc.td - Describe the Sparc Target Machine -------*- tablegen -*-===//
+//
// The LLVM Compiler Infrastructure
//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
//===----------------------------------------------------------------------===//
//
//
// Target-independent interfaces which we are implementing
//===----------------------------------------------------------------------===//
-include "../Target.td"
+include "llvm/Target/Target.td"
//===----------------------------------------------------------------------===//
-// PowerPC Subtarget features.
+// SPARC Subtarget features.
//
-def Feature64Bit : SubtargetFeature<"64bit", "bool", "Is64Bit",
- "Enable 64-bit instructions">;
-
-
-//===----------------------------------------------------------------------===//
-// Register File Description
-//===----------------------------------------------------------------------===//
-
-include "SparcV8RegisterInfo.td"
+def FeatureV9
+ : SubtargetFeature<"v9", "IsV9", "true",
+ "Enable SPARC-V9 instructions">;
+def FeatureV8Deprecated
+ : SubtargetFeature<"deprecated-v8", "V8DeprecatedInsts", "true",
+ "Enable deprecated V8 instructions in V9 mode">;
+def FeatureVIS
+ : SubtargetFeature<"vis", "IsVIS", "true",
+ "Enable UltraSPARC Visual Instruction Set extensions">;
//===----------------------------------------------------------------------===//
-// Instruction Descriptions
+// Register File, Calling Conv, Instruction Descriptions
//===----------------------------------------------------------------------===//
-include "SparcV8InstrInfo.td"
+include "SparcRegisterInfo.td"
+include "SparcCallingConv.td"
+include "SparcInstrInfo.td"
-def SparcV8InstrInfo : InstrInfo {
- let PHIInst = PHI;
-
- // Define how we want to layout our target-specific information field.
- let TSFlagsFields = [];
- let TSFlagsShifts = [];
-}
+def SparcInstrInfo : InstrInfo;
//===----------------------------------------------------------------------===//
// SPARC processors supported.
//===----------------------------------------------------------------------===//
-def : Processor<"generic", NoItineraries, []>;
-def : Processor<"v8", NoItineraries, []>;
-def : Processor<"v9", NoItineraries, [Feature64Bit]>;
+class Proc<string Name, list<SubtargetFeature> Features>
+ : Processor<Name, NoItineraries, Features>;
+
+def : Proc<"generic", []>;
+def : Proc<"v8", []>;
+def : Proc<"supersparc", []>;
+def : Proc<"sparclite", []>;
+def : Proc<"f934", []>;
+def : Proc<"hypersparc", []>;
+def : Proc<"sparclite86x", []>;
+def : Proc<"sparclet", []>;
+def : Proc<"tsc701", []>;
+def : Proc<"v9", [FeatureV9]>;
+def : Proc<"ultrasparc", [FeatureV9, FeatureV8Deprecated]>;
+def : Proc<"ultrasparc3", [FeatureV9, FeatureV8Deprecated]>;
+def : Proc<"ultrasparc3-vis", [FeatureV9, FeatureV8Deprecated, FeatureVIS]>;
+
//===----------------------------------------------------------------------===//
// Declare the target which we are implementing
//===----------------------------------------------------------------------===//
-def SparcV8 : Target {
- // Pointers are 32-bits in size.
- let PointerType = i32;
-
- // FIXME: Specify callee-saved registers
- let CalleeSavedRegisters = [];
-
+def Sparc : Target {
// Pull in Instruction Info:
- let InstructionSet = SparcV8InstrInfo;
+ let InstructionSet = SparcInstrInfo;
}