Some ARM implementaions, e.g. A-series, does return stack prediction. That is,

[oota-llvm.git] / lib / Target / Sparc / Sparc.td

diff --git a/lib/Target/Sparc/Sparc.td b/lib/Target/Sparc/Sparc.td
index 1646e0e1f9649459fefd60bfef2ca6f8b2d5ff29..611f8e8129f41d92ccfbdc223fb262c6da5ff2f1 100644 (file)
--- a/lib/Target/Sparc/Sparc.td
+++ b/lib/Target/Sparc/Sparc.td
@@ -1,10 +1,10 @@
-//===- Sparc.td - Describe the Sparc Target Machine -------------*- C++ -*-===//
-// 
+//===-- Sparc.td - Describe the Sparc Target Machine -------*- tablegen -*-===//
+//
 //                     The LLVM Compiler Infrastructure
 //
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
 //===----------------------------------------------------------------------===//
 //
 //
@@ -14,7 +14,7 @@
 // Target-independent interfaces which we are implementing
 //===----------------------------------------------------------------------===//
 
-include "../Target.td"
+include "llvm/Target/Target.td"
 
 //===----------------------------------------------------------------------===//
 // SPARC Subtarget features.
@@ -31,22 +31,14 @@ def FeatureVIS
                      "Enable UltraSPARC Visual Instruction Set extensions">;
 
 //===----------------------------------------------------------------------===//
-// Register File Description
+// Register File, Calling Conv, Instruction Descriptions
 //===----------------------------------------------------------------------===//
 
 include "SparcRegisterInfo.td"
-
-//===----------------------------------------------------------------------===//
-// Instruction Descriptions
-//===----------------------------------------------------------------------===//
-
+include "SparcCallingConv.td"
 include "SparcInstrInfo.td"
 
-def SparcInstrInfo : InstrInfo {
-  // Define how we want to layout our target-specific information field.
-  let TSFlagsFields = [];
-  let TSFlagsShifts = [];
-}
+def SparcInstrInfo : InstrInfo;
 
 //===----------------------------------------------------------------------===//
 // SPARC processors supported.