Make the logic for determining function alignment more explicit. No functionality...

[oota-llvm.git] / lib / Target / Sparc / README.txt

diff --git a/lib/Target/Sparc/README.txt b/lib/Target/Sparc/README.txt
index f4097b591acb0018cea6293c79c0c12183f1168e..b4991fe5790b705e6dfa5a8e4bfc5aa351ded1ea 100644 (file)
--- a/lib/Target/Sparc/README.txt
+++ b/lib/Target/Sparc/README.txt
@@ -1,41 +1,59 @@
 
-SparcV8 backend skeleton
-------------------------
-
-This directory houses a 32-bit SPARC V8 backend employing an expander-based
-instruction selector.  It is not yet functionally complete.  Watch
-this space for more news coming soon!
-
-Current expected test failures
-------------------------------
-
-All SingleSource/Benchmarks tests are expected to pass.  Currently, all
-C++ tests are expected to fail.  Here are the known SingleSource failures:
-
-       UnitTests/SetjmpLongjmp/C++/C++Catch
-       UnitTests/SetjmpLongjmp/C++/SimpleC++Test
-       Regression/C++/EH/ConditionalExpr
-       Regression/C++/EH/ctor_dtor_count-2
-       Regression/C++/EH/ctor_dtor_count
-       Regression/C++/EH/exception_spec_test
-       Regression/C++/EH/function_try_block
-       Regression/C++/EH/simple_rethrow
-       Regression/C++/EH/simple_throw
-       Regression/C++/EH/throw_rethrow_test
-       CustomChecked/oopack_v1p8
-
-Here are some known MultiSource test failures - this is probably not a
-complete list right now.
-
-       burg siod lambda make_dparser hbd treecc hexxagon fhourstones
-       bisect testtrie eks imp bh power anagram bc distray
-
 To-do
 -----
 
-* support shifts on longs
-* support casting 64-bit integers to FP types
-* support FP rem
-
-$Date$
-
+* Keep the address of the constant pool in a register instead of forming its
+  address all of the time.
+* We can fold small constant offsets into the %hi/%lo references to constant
+  pool addresses as well.
+* When in V9 mode, register allocate %icc[0-3].
+* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
+* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
+  not clear how to write a pattern for this though:
+
+float %t1(int %a, int* %p) {
+        %C = seteq int %a, 0
+        br bool %C, label %T, label %F
+T:
+        store int 123, int* %p
+        br label %F
+F:
+        ret float undef
+}
+
+codegens to this:
+
+t1:
+        save -96, %o6, %o6
+1)      subcc %i0, 0, %l0
+1)      bne .LBBt1_2    ! F
+        nop
+.LBBt1_1:       ! T
+        or %g0, 123, %l0
+        st %l0, [%i1]
+.LBBt1_2:       ! F
+        restore %g0, %g0, %g0
+        retl
+        nop
+
+1) should be replaced with a brz in V9 mode.
+
+* Same as above, but emit conditional move on register zero (p192) in V9 
+  mode.  Testcase:
+
+int %t1(int %a, int %b) {
+        %C = seteq int %a, 0
+        %D = select bool %C, int %a, int %b
+        ret int %D
+}
+
+* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling 
+  with the Y register, if they are faster.
+
+* Codegen bswap(load)/store(bswap) -> load/store ASI
+
+* Implement frame pointer elimination, e.g. eliminate save/restore for 
+  leaf fns.
+* Fill delay slots
+
+* Implement JIT support