Instead of littering asserts throughout the code after every call to

[oota-llvm.git] / lib / Target / Sparc / README.txt

diff --git a/lib/Target/Sparc/README.txt b/lib/Target/Sparc/README.txt
index 5ec8da8029abfde07e7dd0bd1993f0c80d93d1f5..34e68cfa78f7ca67f25a7189e0fada894a77b234 100644 (file)
--- a/lib/Target/Sparc/README.txt
+++ b/lib/Target/Sparc/README.txt
@@ -7,6 +7,7 @@ To-do
 * We can fold small constant offsets into the %hi/%lo references to constant
   pool addresses as well.
 * When in V9 mode, register allocate %icc[0-3].
+* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
 * Emit the 'Branch on Integer Register with Prediction' instructions.  It's
   not clear how to write a pattern for this though:
 
@@ -37,4 +38,24 @@ t1:
 
 1) should be replaced with a brz in V9 mode.
 
-* Same as above, but emit conditional move on register zero (p192) in V9 mode.
+* Same as above, but emit conditional move on register zero (p192) in V9
+  mode.  Testcase:
+
+int %t1(int %a, int %b) {
+        %C = seteq int %a, 0
+        %D = select bool %C, int %a, int %b
+        ret int %D
+}
+
+* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling
+  with the Y register, if they are faster.
+
+* Codegen bswap(load)/store(bswap) -> load/store ASI
+
+* Implement frame pointer elimination, e.g. eliminate save/restore for
+  leaf fns.
+* Fill delay slots
+
+* Implement JIT support
+
+* Use %g0 directly to materialize 0. No instruction is required.