AMDGPU/SI: Add SI Machine Scheduler

[oota-llvm.git] / lib / Target / Sparc / Makefile

diff --git a/lib/Target/Sparc/Makefile b/lib/Target/Sparc/Makefile
index b6f6aaf0fcb064b6b0b8d99c92156d7063bfcb30..c2a95b47151ab11dadb4326aaf212a5cd2e0086f 100644 (file)
--- a/lib/Target/Sparc/Makefile
+++ b/lib/Target/Sparc/Makefile
@@ -1,21 +1,24 @@
 ##===- lib/Target/Sparc/Makefile ---------------------------*- Makefile -*-===##
-# 
+#
 #                     The LLVM Compiler Infrastructure
 #
-# This file was developed by the LLVM research group and is distributed under
-# the University of Illinois Open Source License. See LICENSE.TXT for details.
-# 
+# This file is distributed under the University of Illinois Open Source
+# License. See LICENSE.TXT for details.
+#
 ##===----------------------------------------------------------------------===##
+
 LEVEL = ../../..
-LIBRARYNAME = LLVMSparc
+LIBRARYNAME = LLVMSparcCodeGen
 TARGET = Sparc
-EXTRA_DIST = README.txt
 
 # Make sure that tblgen is run, first thing.
-BUILT_SOURCES = SparcGenRegisterInfo.h.inc SparcGenRegisterNames.inc \
-                SparcGenRegisterInfo.inc SparcGenInstrNames.inc \
-                SparcGenInstrInfo.inc SparcGenAsmWriter.inc \
-                SparcGenDAGISel.inc SparcGenSubtarget.inc
+BUILT_SOURCES = SparcGenRegisterInfo.inc SparcGenInstrInfo.inc \
+               SparcGenAsmWriter.inc SparcGenAsmMatcher.inc \
+               SparcGenDAGISel.inc SparcGenDisassemblerTables.inc \
+               SparcGenSubtargetInfo.inc SparcGenCallingConv.inc \
+               SparcGenMCCodeEmitter.inc
+
+DIRS = InstPrinter AsmParser Disassembler TargetInfo MCTargetDesc
 
 include $(LEVEL)/Makefile.common