if (VA.isMemLoc()) {
VT = Ins[i].VT;
EVT MemVT = Splits[i].VT;
+ const unsigned Offset = 36 + VA.getLocMemOffset();
// The first 36 bytes of the input buffer contains information about
// thread group and global sizes.
SDValue Arg = LowerParameter(DAG, VT, MemVT, DL, DAG.getRoot(),
- 36 + VA.getLocMemOffset(),
- Ins[i].Flags.isSExt());
+ Offset, Ins[i].Flags.isSExt());
const PointerType *ParamTy =
dyn_cast<PointerType>(FType->getParamType(Ins[i].OrigArgIndex));
}
InVals.push_back(Arg);
+ Info->ABIArgOffset = Offset + MemVT.getStoreSize();
continue;
}
assert(VA.isRegLoc() && "Parameter must be in a register!");
case Intrinsic::r600_read_local_size_z:
return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
SI::KernelInputOffsets::LOCAL_SIZE_Z, false);
+
+ case Intrinsic::AMDGPU_read_workdim:
+ return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
+ MF.getInfo<SIMachineFunctionInfo>()->ABIArgOffset,
+ false);
+
case Intrinsic::r600_read_tgid_x:
return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
TRI->getPreloadedValue(MF, SIRegisterInfo::TGID_X), VT);
}
}
-/// \brief Legalize INSERT_SUBREG instructions with frame index operands.
-/// LLVM assumes that all INSERT_SUBREG inputs are registers.
-static void legalizeInsertSubreg(MachineSDNode *InsertSubreg,
- SelectionDAG &DAG) {
-
- assert(InsertSubreg->getMachineOpcode() == AMDGPU::INSERT_SUBREG);
+/// \brief Legalize target independent instructions (e.g. INSERT_SUBREG)
+/// with frame index operands.
+/// LLVM assumes that inputs are to these instructions are registers.
+void SITargetLowering::legalizeTargetIndependentNode(SDNode *Node,
+ SelectionDAG &DAG) const {
SmallVector<SDValue, 8> Ops;
- for (unsigned i = 0; i < 2; ++i) {
- if (!isa<FrameIndexSDNode>(InsertSubreg->getOperand(i))) {
- Ops.push_back(InsertSubreg->getOperand(i));
+ for (unsigned i = 0; i < Node->getNumOperands(); ++i) {
+ if (!isa<FrameIndexSDNode>(Node->getOperand(i))) {
+ Ops.push_back(Node->getOperand(i));
continue;
}
- SDLoc DL(InsertSubreg);
+ SDLoc DL(Node);
Ops.push_back(SDValue(DAG.getMachineNode(AMDGPU::S_MOV_B32, DL,
- InsertSubreg->getOperand(i).getValueType(),
- InsertSubreg->getOperand(i)), 0));
+ Node->getOperand(i).getValueType(),
+ Node->getOperand(i)), 0));
}
- DAG.UpdateNodeOperands(InsertSubreg, Ops[0], Ops[1],
- InsertSubreg->getOperand(2));
+ DAG.UpdateNodeOperands(Node, Ops);
}
/// \brief Fold the instructions after selecting them.