#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/Support/Debug.h"
+#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
using namespace llvm;
unsigned SrcReg = Copy.getOperand(1).getReg();
unsigned SrcSubReg = Copy.getOperand(1).getSubReg();
const TargetRegisterClass *DstRC = MRI.getRegClass(DstReg);
+ const TargetRegisterClass *SrcRC;
if (!TargetRegisterInfo::isVirtualRegister(SrcReg) ||
DstRC == &AMDGPU::M0RegRegClass)
return false;
- const TargetRegisterClass *SrcRC = TRI->getSubRegClass(
- MRI.getRegClass(SrcReg), SrcSubReg);
-
- return TRI->isSGPRClass(DstRC) &&
- !TRI->getCommonSubClass(DstRC, SrcRC);
+ SrcRC = inferRegClassFromDef(TRI, MRI, SrcReg, SrcSubReg);
+ return TRI->isSGPRClass(DstRC) && TRI->hasVGPRs(SrcRC);
}
bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) {
!hasVGPROperands(MI, TRI))
continue;
- DEBUG(dbgs() << "Fixing REG_SEQUENCE: \n");
+ DEBUG(dbgs() << "Fixing REG_SEQUENCE:\n");
DEBUG(MI.print(dbgs()));
TII->moveToVALU(MI);
- TII->legalizeOperands(&MI);
break;
}
}