R600: Fix an infinite loop when trying to reorganize export/tex vector input

[oota-llvm.git] / lib / Target / R600 / SIFixSGPRCopies.cpp

diff --git a/lib/Target/R600/SIFixSGPRCopies.cpp b/lib/Target/R600/SIFixSGPRCopies.cpp
index 655db5b01daad5cb0ea18a0ea6d8c1ff8f48a91c..3370c7955bc75c56dadb0f9ea14953a4d29e762b 100644 (file)
--- a/lib/Target/R600/SIFixSGPRCopies.cpp
+++ b/lib/Target/R600/SIFixSGPRCopies.cpp
@@ -23,9 +23,9 @@
 ///    %vreg3 <vsrc> = COPY %vreg2 <vgpr>
 ///  BB2:
 ///    %vreg4 <vsrc> = PHI %vreg1 <vsrc>, <BB#0>, %vreg3 <vrsc>, <BB#1>
-///    %vreg5 <vgpr> = VECTOR_INST %vreg4 <vsrc> 
+///    %vreg5 <vgpr> = VECTOR_INST %vreg4 <vsrc>
+///
 ///
-/// 
 /// The coalescer will begin at BB0 and eliminate its copy, then the resulting
 /// code will look like this:
 ///
@@ -43,7 +43,7 @@
 /// Now that the result of the PHI instruction is an SGPR, the register
 /// allocator is now forced to constrain the register class of %vreg3 to
 /// <sgpr> so we end up with final code like this:
-/// 
+///
 /// BB0:
 ///   %vreg0 <sgpr> = SCALAR_INST
 ///    ...
@@ -55,7 +55,7 @@
 ///   %vreg4 <sgpr> = PHI %vreg0 <sgpr>, <BB#0>, %vreg3 <sgpr>, <BB#1>
 ///   %vreg5 <vgpr> = VECTOR_INST %vreg4 <sgpr>
 ///
-/// Now this code contains an illegal copy from a VGPR to an SGPR. 
+/// Now this code contains an illegal copy from a VGPR to an SGPR.
 ///
 /// In order to avoid this problem, this pass searches for PHI instructions
 /// which define a <vsrc> register and constrains its definition class to
@@ -72,6 +72,7 @@
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/Support/Debug.h"
+#include "llvm/Support/raw_ostream.h"
 #include "llvm/Target/TargetMachine.h"
 
 using namespace llvm;
@@ -127,7 +128,7 @@ static bool hasVGPROperands(const MachineInstr &MI, const SIRegisterInfo *TRI) {
 
 /// This functions walks the use list of Reg until it finds an Instruction
 /// that isn't a COPY returns the register class of that instruction.
-/// \param[out] The register defined by the first non-COPY instruction.
+/// \return The register defined by the first non-COPY instruction.
 const TargetRegisterClass *SIFixSGPRCopies::inferRegClassFromUses(
                                                  const SIRegisterInfo *TRI,
                                                  const MachineRegisterInfo &MRI,
@@ -180,16 +181,14 @@ bool SIFixSGPRCopies::isVGPRToSGPRCopy(const MachineInstr &Copy,
   unsigned SrcReg = Copy.getOperand(1).getReg();
   unsigned SrcSubReg = Copy.getOperand(1).getSubReg();
   const TargetRegisterClass *DstRC = MRI.getRegClass(DstReg);
+  const TargetRegisterClass *SrcRC;
 
   if (!TargetRegisterInfo::isVirtualRegister(SrcReg) ||
       DstRC == &AMDGPU::M0RegRegClass)
     return false;
 
-  const TargetRegisterClass *SrcRC = TRI->getSubRegClass(
-      MRI.getRegClass(SrcReg), SrcSubReg);
-
-  return TRI->isSGPRClass(DstRC) &&
-         !TRI->getCommonSubClass(DstRC, SrcRC);
+  SrcRC = inferRegClassFromDef(TRI, MRI, SrcReg, SrcSubReg);
+  return TRI->isSGPRClass(DstRC) && TRI->hasVGPRs(SrcRC);
 }
 
 bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) {
@@ -251,11 +250,10 @@ bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) {
             !hasVGPROperands(MI, TRI))
           continue;
 
-        DEBUG(dbgs() << "Fixing REG_SEQUENCE: \n");
+        DEBUG(dbgs() << "Fixing REG_SEQUENCE:\n");
         DEBUG(MI.print(dbgs()));
 
         TII->moveToVALU(MI);
-        TII->legalizeOperands(&MI);
         break;
       }
       }