Revert "R600: Non vector only instruction can be scheduled on trans unit"

[oota-llvm.git] / lib / Target / R600 / R600MachineScheduler.h

diff --git a/lib/Target/R600/R600MachineScheduler.h b/lib/Target/R600/R600MachineScheduler.h
index 4dedf70d5f75764000c4770d7b105cd9360b27a4..f8965d8998a4cac8bd66834203c9f524cf17d99f 100644 (file)
--- a/lib/Target/R600/R600MachineScheduler.h
+++ b/lib/Target/R600/R600MachineScheduler.h
@@ -46,6 +46,7 @@ class R600SchedStrategy : public MachineSchedStrategy {
     AluT_W,
     AluT_XYZW,
     AluPredX,
+    AluTrans,
     AluDiscarded, // LLVM Instructions that are going to be eliminated
     AluLast
   };
@@ -54,11 +55,15 @@ class R600SchedStrategy : public MachineSchedStrategy {
   std::vector<SUnit *> AvailableAlus[AluLast];
   std::vector<SUnit *> UnscheduledARDefs;
   std::vector<SUnit *> UnscheduledARUses;
+  std::vector<SUnit *> PhysicalRegCopy;
 
   InstKind CurInstKind;
   int CurEmitted;
   InstKind NextInstKind;
 
+  unsigned AluInstCount;
+  unsigned FetchInstCount;
+
   int InstKindLimit[IDLast];
 
   int OccupedSlotsMask;
@@ -84,7 +89,7 @@ private:
   bool regBelongsToClass(unsigned Reg, const TargetRegisterClass *RC) const;
   AluKind getAluKind(SUnit *SU) const;
   void LoadAlu();
-  bool isAvailablesAluEmpty() const;
+  unsigned AvailablesAluCount() const;
   SUnit *AttemptFillSlot (unsigned Slot);
   void PrepareNextSlot();
   SUnit *PopInst(std::vector<SUnit*> &Q);