// This file describes the AMDIL instructions in TableGen format.
//
//===----------------------------------------------------------------------===//
-// AMDIL Instruction Predicate Definitions
-// Predicate that is set to true if the hardware supports double precision
-// divide
-def HasHWDDiv : Predicate<"Subtarget.device()"
- "->getGeneration() > AMDGPUDeviceInfo::HD4XXX && "
- "Subtarget.device()->usesHardware(AMDGPUDeviceInfo::DoubleOps)">;
-
-// Predicate that is set to true if the hardware supports double, but not double
-// precision divide in hardware
-def HasSWDDiv : Predicate<"Subtarget.device()"
- "->getGeneration() == AMDGPUDeviceInfo::HD4XXX &&"
- "Subtarget.device()->usesHardware(AMDGPUDeviceInfo::DoubleOps)">;
-
-// Predicate that is set to true if the hardware support 24bit signed
-// math ops. Otherwise a software expansion to 32bit math ops is used instead.
-def HasHWSign24Bit : Predicate<"Subtarget.device()"
- "->getGeneration() > AMDGPUDeviceInfo::HD5XXX">;
-
-// Predicate that is set to true if 64bit operations are supported or not
-def HasHW64Bit : Predicate<"Subtarget.device()"
- "->usesHardware(AMDGPUDeviceInfo::LongOps)">;
-def HasSW64Bit : Predicate<"Subtarget.device()"
- "->usesSoftware(AMDGPUDeviceInfo::LongOps)">;
-
-// Predicate that is set to true if the timer register is supported
-def HasTmrRegister : Predicate<"Subtarget.device()"
- "->isSupported(AMDGPUDeviceInfo::TmrReg)">;
-// Predicate that is true if we are at least evergreen series
-def HasDeviceIDInst : Predicate<"Subtarget.device()"
- "->getGeneration() >= AMDGPUDeviceInfo::HD5XXX">;
-
-// Predicate that is true if we have region address space.
-def hasRegionAS : Predicate<"Subtarget.device()"
- "->usesHardware(AMDGPUDeviceInfo::RegionMem)">;
-
-// Predicate that is false if we don't have region address space.
-def noRegionAS : Predicate<"!Subtarget.device()"
- "->isSupported(AMDGPUDeviceInfo::RegionMem)">;
-
-
-// Predicate that is set to true if 64bit Mul is supported in the IL or not
-def HasHW64Mul : Predicate<"Subtarget.calVersion()"
- ">= CAL_VERSION_SC_139"
- "&& Subtarget.device()"
- "->getGeneration() >="
- "AMDGPUDeviceInfo::HD5XXX">;
-def HasSW64Mul : Predicate<"Subtarget.calVersion()"
- "< CAL_VERSION_SC_139">;
-// Predicate that is set to true if 64bit Div/Mod is supported in the IL or not
-def HasHW64DivMod : Predicate<"Subtarget.device()"
- "->usesHardware(AMDGPUDeviceInfo::HW64BitDivMod)">;
-def HasSW64DivMod : Predicate<"Subtarget.device()"
- "->usesSoftware(AMDGPUDeviceInfo::HW64BitDivMod)">;
-
-// Predicate that is set to true if 64bit pointer are used.
-def Has64BitPtr : Predicate<"Subtarget.is64bit()">;
-def Has32BitPtr : Predicate<"!Subtarget.is64bit()">;
//===--------------------------------------------------------------------===//
// Custom Operands
//===--------------------------------------------------------------------===//
//===--------------------------------------------------------------------===//
// Floating point math functions
def IL_div_inf : SDNode<"AMDGPUISD::DIV_INF", SDTIL_GenBinaryOp>;
-def IL_mad : SDNode<"AMDGPUISD::MAD", SDTIL_GenTernaryOp>;
//===----------------------------------------------------------------------===//
// Integer functions
// Multiclass Instruction formats
//===--------------------------------------------------------------------===//
// Multiclass that handles branch instructions
-multiclass BranchConditional<SDNode Op> {
+multiclass BranchConditional<SDNode Op, RegisterClass rci, RegisterClass rcf> {
def _i32 : ILFormat<(outs),
- (ins brtarget:$target, GPRI32:$src0),
+ (ins brtarget:$target, rci:$src0),
"; i32 Pseudo branch instruction",
- [(Op bb:$target, GPRI32:$src0)]>;
+ [(Op bb:$target, (i32 rci:$src0))]>;
def _f32 : ILFormat<(outs),
- (ins brtarget:$target, GPRF32:$src0),
+ (ins brtarget:$target, rcf:$src0),
"; f32 Pseudo branch instruction",
- [(Op bb:$target, GPRF32:$src0)]>;
+ [(Op bb:$target, (f32 rcf:$src0))]>;
}
// Only scalar types should generate flow control
// Intrinsics support
//===--------------------------------------------------------------------===//
include "AMDILIntrinsics.td"
-
-//===--------------------------------------------------------------------===//
-// Instructions support
-//===--------------------------------------------------------------------===//
-//===---------------------------------------------------------------------===//
-// Custom Inserter for Branches and returns, this eventually will be a
-// seperate pass
-//===---------------------------------------------------------------------===//
-let isTerminator = 1, usesCustomInserter = 1, isBranch = 1, isBarrier = 1 in {
- def BRANCH : ILFormat<(outs), (ins brtarget:$target),
- "; Pseudo unconditional branch instruction",
- [(br bb:$target)]>;
- defm BRANCH_COND : BranchConditional<IL_brcond>;
-}
-
-//===---------------------------------------------------------------------===//
-// Flow and Program control Instructions
-//===---------------------------------------------------------------------===//
-let isTerminator=1 in {
- def SWITCH : ILFormat< (outs), (ins GPRI32:$src),
- !strconcat("SWITCH", " $src"), []>;
- def CASE : ILFormat< (outs), (ins GPRI32:$src),
- !strconcat("CASE", " $src"), []>;
- def BREAK : ILFormat< (outs), (ins),
- "BREAK", []>;
- def CONTINUE : ILFormat< (outs), (ins),
- "CONTINUE", []>;
- def DEFAULT : ILFormat< (outs), (ins),
- "DEFAULT", []>;
- def ELSE : ILFormat< (outs), (ins),
- "ELSE", []>;
- def ENDSWITCH : ILFormat< (outs), (ins),
- "ENDSWITCH", []>;
- def ENDMAIN : ILFormat< (outs), (ins),
- "ENDMAIN", []>;
- def END : ILFormat< (outs), (ins),
- "END", []>;
- def ENDFUNC : ILFormat< (outs), (ins),
- "ENDFUNC", []>;
- def ENDIF : ILFormat< (outs), (ins),
- "ENDIF", []>;
- def WHILELOOP : ILFormat< (outs), (ins),
- "WHILE", []>;
- def ENDLOOP : ILFormat< (outs), (ins),
- "ENDLOOP", []>;
- def FUNC : ILFormat< (outs), (ins),
- "FUNC", []>;
- def RETDYN : ILFormat< (outs), (ins),
- "RET_DYN", []>;
- // This opcode has custom swizzle pattern encoded in Swizzle Encoder
- defm IF_LOGICALNZ : BranchInstr<"IF_LOGICALNZ">;
- // This opcode has custom swizzle pattern encoded in Swizzle Encoder
- defm IF_LOGICALZ : BranchInstr<"IF_LOGICALZ">;
- // This opcode has custom swizzle pattern encoded in Swizzle Encoder
- defm BREAK_LOGICALNZ : BranchInstr<"BREAK_LOGICALNZ">;
- // This opcode has custom swizzle pattern encoded in Swizzle Encoder
- defm BREAK_LOGICALZ : BranchInstr<"BREAK_LOGICALZ">;
- // This opcode has custom swizzle pattern encoded in Swizzle Encoder
- defm CONTINUE_LOGICALNZ : BranchInstr<"CONTINUE_LOGICALNZ">;
- // This opcode has custom swizzle pattern encoded in Swizzle Encoder
- defm CONTINUE_LOGICALZ : BranchInstr<"CONTINUE_LOGICALZ">;
- defm IFC : BranchInstr2<"IFC">;
- defm BREAKC : BranchInstr2<"BREAKC">;
- defm CONTINUEC : BranchInstr2<"CONTINUEC">;
-}
projects / oota-llvm.git / blobdiff