return SelectMUBUFAddr64(Addr, SRsrc, VAddr, Offset);
}
-static SDValue buildSMovImm32(SelectionDAG *DAG, SDLoc DL, uint64_t Val) {
- SDValue K = DAG->getTargetConstant(Val, MVT::i32);
- return SDValue(DAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32, K), 0);
-}
-
-static SDValue buildRSRC(SelectionDAG *DAG, SDLoc DL, SDValue Ptr,
- uint32_t RsrcDword1, uint64_t RsrcDword2And3) {
- SDValue PtrLo = DAG->getTargetExtractSubreg(AMDGPU::sub0, DL, MVT::i32, Ptr);
- SDValue PtrHi = DAG->getTargetExtractSubreg(AMDGPU::sub1, DL, MVT::i32, Ptr);
- if (RsrcDword1) {
- PtrHi = SDValue(DAG->getMachineNode(AMDGPU::S_OR_B32, DL, MVT::i32, PtrHi,
- DAG->getConstant(RsrcDword1, MVT::i32)), 0);
- }
-
- SDValue DataLo = buildSMovImm32(DAG, DL,
- RsrcDword2And3 & UINT64_C(0xFFFFFFFF));
- SDValue DataHi = buildSMovImm32(DAG, DL, RsrcDword2And3 >> 32);
-
- const SDValue Ops[] = {
- DAG->getTargetConstant(AMDGPU::SReg_128RegClassID, MVT::i32),
- PtrLo,
- DAG->getTargetConstant(AMDGPU::sub0, MVT::i32),
- PtrHi,
- DAG->getTargetConstant(AMDGPU::sub1, MVT::i32),
- DataLo,
- DAG->getTargetConstant(AMDGPU::sub2, MVT::i32),
- DataHi,
- DAG->getTargetConstant(AMDGPU::sub3, MVT::i32)
- };
-
- return SDValue(DAG->getMachineNode(AMDGPU::REG_SEQUENCE, DL,
- MVT::v4i32, Ops), 0);
-}
-
-/// \brief Return a resource descriptor with the 'Add TID' bit enabled
-/// The TID (Thread ID) is multipled by the stride value (bits [61:48]
-/// of the resource descriptor) to create an offset, which is added to the
-/// resource ponter.
-static SDValue buildScratchRSRC(SelectionDAG *DAG, SDLoc DL, SDValue Ptr) {
-
- uint64_t Rsrc = AMDGPU::RSRC_DATA_FORMAT | AMDGPU::RSRC_TID_ENABLE |
- 0xffffffff; // Size
-
- return buildRSRC(DAG, DL, Ptr, 0, Rsrc);
-}
-
bool AMDGPUDAGToDAGISel::SelectMUBUFScratch(SDValue Addr, SDValue &Rsrc,
SDValue &VAddr, SDValue &SOffset,
SDValue &ImmOffset) const {
Lowering.CreateLiveInRegister(*CurDAG, &AMDGPU::SReg_32RegClass,
ScratchOffsetReg, MVT::i32);
- Rsrc = buildScratchRSRC(CurDAG, DL,
- CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
- MRI.getLiveInVirtReg(ScratchPtrReg), MVT::i64));
+ SDValue ScratchPtr =
+ CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
+ MRI.getLiveInVirtReg(ScratchPtrReg), MVT::i64);
+ Rsrc = SDValue(Lowering.buildScratchRSRC(*CurDAG, DL, ScratchPtr), 0);
SOffset = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
MRI.getLiveInVirtReg(ScratchOffsetReg), MVT::i32);
uint64_t Rsrc = AMDGPU::RSRC_DATA_FORMAT |
APInt::getAllOnesValue(32).getZExtValue(); // Size
SDLoc DL(Addr);
- SRsrc = buildRSRC(CurDAG, DL, Ptr, 0, Rsrc);
+
+ const SITargetLowering& Lowering =
+ *static_cast<const SITargetLowering*>(getTargetLowering());
+
+ SRsrc = SDValue(Lowering.buildRSRC(*CurDAG, DL, Ptr, 0, Rsrc), 0);
return true;
}
return false;