-//===-- PowerPCTargetMachine.cpp - Define TargetMachine for PowerPC -------===//
+//===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
//
// The LLVM Compiler Infrastructure
//
//
//===----------------------------------------------------------------------===//
//
+// Top-level implementation for the PowerPC target.
//
//===----------------------------------------------------------------------===//
-#include "PowerPC.h"
-#include "PowerPCTargetMachine.h"
-#include "PowerPCFrameInfo.h"
-#include "PPC32TargetMachine.h"
-#include "PPC64TargetMachine.h"
-#include "PPC32JITInfo.h"
-#include "PPC64JITInfo.h"
+#include "PPC.h"
+#include "PPCTargetAsmInfo.h"
+#include "PPCTargetMachine.h"
#include "llvm/Module.h"
#include "llvm/PassManager.h"
-#include "llvm/Analysis/Verifier.h"
-#include "llvm/CodeGen/IntrinsicLowering.h"
-#include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/CodeGen/Passes.h"
-#include "llvm/Target/TargetOptions.h"
#include "llvm/Target/TargetMachineRegistry.h"
-#include "llvm/Transforms/Scalar.h"
-#include "llvm/Support/CommandLine.h"
-#include <iostream>
using namespace llvm;
-static cl::opt<bool> EnablePPCLSR("enable-lsr-for-ppc", cl::Hidden,
- cl::desc("Enable LSR for PPC (beta)"));
-
namespace {
- const std::string PPC32ID = "PowerPC/32bit";
- const std::string PPC64ID = "PowerPC/64bit";
-
// Register the targets
RegisterTarget<PPC32TargetMachine>
- X("ppc32", " PowerPC 32-bit");
-
-#if 0
+ X("ppc32", " PowerPC 32");
RegisterTarget<PPC64TargetMachine>
- Y("ppc64", " PowerPC 64-bit (unimplemented)");
-#endif
+ Y("ppc64", " PowerPC 64");
}
-PowerPCTargetMachine::PowerPCTargetMachine(const std::string &name,
- IntrinsicLowering *IL,
- const Module &M,
- const TargetData &TD,
- const PowerPCFrameInfo &TFI)
-: TargetMachine(name, IL, TD), FrameInfo(TFI), Subtarget(M) {
- if (TargetDefault == PPCTarget) {
- if (Subtarget.isAIX()) PPCTarget = TargetAIX;
- if (Subtarget.isDarwin()) PPCTarget = TargetDarwin;
- }
+const TargetAsmInfo *PPCTargetMachine::createTargetAsmInfo() const {
+ if (Subtarget.isDarwin())
+ return new DarwinTargetAsmInfo(*this);
+ else
+ return new LinuxTargetAsmInfo(*this);
}
unsigned PPC32TargetMachine::getJITMatchQuality() {
-#if defined(__POWERPC__) || defined (__ppc__) || defined(_POWER)
- return 10;
-#else
- return 0;
+#if defined(__POWERPC__) || defined (__ppc__) || defined(_POWER) || defined(__PPC__)
+ if (sizeof(void*) == 4)
+ return 10;
#endif
+ return 0;
}
-
-/// addPassesToEmitFile - Add passes to the specified pass manager to implement
-/// a static compiler for this target.
-///
-bool PowerPCTargetMachine::addPassesToEmitFile(PassManager &PM,
- std::ostream &Out,
- CodeGenFileType FileType) {
- if (FileType != TargetMachine::AssemblyFile) return true;
-
- bool LP64 = (0 != dynamic_cast<PPC64TargetMachine *>(this));
-
- if (EnablePPCLSR) {
- PM.add(createLoopStrengthReducePass());
- PM.add(createVerifierPass());
- PM.add(createCFGSimplificationPass());
- }
-
- // FIXME: Implement efficient support for garbage collection intrinsics.
- PM.add(createLowerGCPass());
-
- // FIXME: Implement the invoke/unwind instructions!
- PM.add(createLowerInvokePass());
-
- // FIXME: Implement the switch instruction in the instruction selector!
- PM.add(createLowerSwitchPass());
-
- PM.add(createLowerConstantExpressionsPass());
-
- // Make sure that no unreachable blocks are instruction selected.
- PM.add(createUnreachableBlockEliminationPass());
-
- // Default to pattern ISel
- if (LP64)
- PM.add(createPPC64ISelPattern(*this));
- else if (PatternISelTriState == 0)
- PM.add(createPPC32ISelSimple(*this));
- else
- PM.add(createPPC32ISelPattern(*this));
-
- if (PrintMachineCode)
- PM.add(createMachineFunctionPrinterPass(&std::cerr));
-
- PM.add(createRegisterAllocator());
-
- if (PrintMachineCode)
- PM.add(createMachineFunctionPrinterPass(&std::cerr));
-
- PM.add(createPrologEpilogCodeInserter());
-
- // Must run branch selection immediately preceding the asm printer
- PM.add(createPPCBranchSelectionPass());
-
- // Decide which asm printer to use. If the user has not specified one on
- // the command line, choose whichever one matches the default (current host).
- switch (PPCTarget) {
- case TargetAIX:
- PM.add(createAIXAsmPrinter(Out, *this));
- break;
- case TargetDefault:
- case TargetDarwin:
- PM.add(createDarwinAsmPrinter(Out, *this));
- break;
- }
-
- PM.add(createMachineCodeDeleter());
- return false;
-}
-
-void PowerPCJITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
- // The JIT does not support or need PIC.
- PICEnabled = false;
-
- bool LP64 = (0 != dynamic_cast<PPC64TargetMachine *>(&TM));
-
- if (EnablePPCLSR) {
- PM.add(createLoopStrengthReducePass());
- PM.add(createCFGSimplificationPass());
- }
-
- // FIXME: Implement efficient support for garbage collection intrinsics.
- PM.add(createLowerGCPass());
-
- // FIXME: Implement the invoke/unwind instructions!
- PM.add(createLowerInvokePass());
-
- // FIXME: Implement the switch instruction in the instruction selector!
- PM.add(createLowerSwitchPass());
-
- PM.add(createLowerConstantExpressionsPass());
-
- // Make sure that no unreachable blocks are instruction selected.
- PM.add(createUnreachableBlockEliminationPass());
-
- // Default to pattern ISel
- if (LP64)
- PM.add(createPPC64ISelPattern(TM));
- else if (PatternISelTriState == 0)
- PM.add(createPPC32ISelSimple(TM));
- else
- PM.add(createPPC32ISelPattern(TM));
-
- PM.add(createRegisterAllocator());
- PM.add(createPrologEpilogCodeInserter());
-
- // Must run branch selection immediately preceding the asm printer
- PM.add(createPPCBranchSelectionPass());
-
- if (PrintMachineCode)
- PM.add(createMachineFunctionPrinterPass(&std::cerr));
+unsigned PPC64TargetMachine::getJITMatchQuality() {
+#if defined(__POWERPC__) || defined (__ppc__) || defined(_POWER) || defined(__PPC__)
+ if (sizeof(void*) == 8)
+ return 10;
+#endif
+ return 0;
}
-/// PowerPCTargetMachine ctor - Create an ILP32 architecture model
-///
-PPC32TargetMachine::PPC32TargetMachine(const Module &M, IntrinsicLowering *IL)
- : PowerPCTargetMachine(PPC32ID, IL, M,
- TargetData(PPC32ID,false,4,4,4,4,4,4,2,1,1),
- PowerPCFrameInfo(*this, false)), JITInfo(*this) {}
-
-/// PPC64TargetMachine ctor - Create a LP64 architecture model
-///
-PPC64TargetMachine::PPC64TargetMachine(const Module &M, IntrinsicLowering *IL)
- : PowerPCTargetMachine(PPC64ID, IL, M,
- TargetData(PPC64ID,false,8,4,4,4,4,4,2,1,1),
- PowerPCFrameInfo(*this, true)) {}
-
unsigned PPC32TargetMachine::getModuleMatchQuality(const Module &M) {
// We strongly match "powerpc-*".
std::string TT = M.getTargetTriple();
if (TT.size() >= 8 && std::string(TT.begin(), TT.begin()+8) == "powerpc-")
return 20;
-
+
if (M.getEndianness() == Module::BigEndian &&
M.getPointerSize() == Module::Pointer32)
return 10; // Weak match
else if (M.getEndianness() != Module::AnyEndianness ||
M.getPointerSize() != Module::AnyPointerSize)
return 0; // Match for some other target
-
+
return getJITMatchQuality()/2;
}
unsigned PPC64TargetMachine::getModuleMatchQuality(const Module &M) {
+ // We strongly match "powerpc64-*".
+ std::string TT = M.getTargetTriple();
+ if (TT.size() >= 10 && std::string(TT.begin(), TT.begin()+10) == "powerpc64-")
+ return 20;
+
if (M.getEndianness() == Module::BigEndian &&
M.getPointerSize() == Module::Pointer64)
- return 10; // Direct match
+ return 10; // Weak match
else if (M.getEndianness() != Module::AnyEndianness ||
M.getPointerSize() != Module::AnyPointerSize)
return 0; // Match for some other target
-
+
return getJITMatchQuality()/2;
}
+
+
+PPCTargetMachine::PPCTargetMachine(const Module &M, const std::string &FS,
+ bool is64Bit)
+ : Subtarget(*this, M, FS, is64Bit),
+ DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this),
+ FrameInfo(*this, is64Bit), JITInfo(*this, is64Bit), TLInfo(*this),
+ InstrItins(Subtarget.getInstrItineraryData()), MachOWriterInfo(*this) {
+
+ if (getRelocationModel() == Reloc::Default)
+ if (Subtarget.isDarwin())
+ setRelocationModel(Reloc::DynamicNoPIC);
+ else
+ setRelocationModel(Reloc::Static);
+}
+
+/// Override this for PowerPC. Tail merging happily breaks up instruction issue
+/// groups, which typically degrades performance.
+const bool PPCTargetMachine::DoTailMergeDefault() const { return false; }
+
+PPC32TargetMachine::PPC32TargetMachine(const Module &M, const std::string &FS)
+ : PPCTargetMachine(M, FS, false) {
+}
+
+
+PPC64TargetMachine::PPC64TargetMachine(const Module &M, const std::string &FS)
+ : PPCTargetMachine(M, FS, true) {
+}
+
+
+//===----------------------------------------------------------------------===//
+// Pass Pipeline Configuration
+//===----------------------------------------------------------------------===//
+
+bool PPCTargetMachine::addInstSelector(FunctionPassManager &PM, bool Fast) {
+ // Install an instruction selector.
+ PM.add(createPPCISelDag(*this));
+ return false;
+}
+
+bool PPCTargetMachine::addPreEmitPass(FunctionPassManager &PM, bool Fast) {
+
+ // Must run branch selection immediately preceding the asm printer.
+ PM.add(createPPCBranchSelectionPass());
+ return false;
+}
+
+bool PPCTargetMachine::addAssemblyEmitter(FunctionPassManager &PM, bool Fast,
+ std::ostream &Out) {
+ PM.add(createPPCAsmPrinterPass(Out, *this));
+ return false;
+}
+
+bool PPCTargetMachine::addCodeEmitter(FunctionPassManager &PM, bool Fast,
+ MachineCodeEmitter &MCE) {
+ // The JIT should use the static relocation model in ppc32 mode, PIC in ppc64.
+ // FIXME: This should be moved to TargetJITInfo!!
+ if (Subtarget.isPPC64()) {
+ // We use PIC codegen in ppc64 mode, because otherwise we'd have to use many
+ // instructions to materialize arbitrary global variable + function +
+ // constant pool addresses.
+ setRelocationModel(Reloc::PIC_);
+ } else {
+ setRelocationModel(Reloc::Static);
+ }
+
+ // Inform the subtarget that we are in JIT mode. FIXME: does this break macho
+ // writing?
+ Subtarget.SetJITMode();
+
+ // Machine code emitter pass for PowerPC.
+ PM.add(createPPCCodeEmitterPass(*this, MCE));
+ return false;
+}
+
+bool PPCTargetMachine::addSimpleCodeEmitter(FunctionPassManager &PM, bool Fast,
+ MachineCodeEmitter &MCE) {
+ // Machine code emitter pass for PowerPC.
+ PM.add(createPPCCodeEmitterPass(*this, MCE));
+ return false;
+}
projects / oota-llvm.git / blobdiff