PowerPC: Use RegisterOperand instead of RegisterClass operands

[oota-llvm.git] / lib / Target / PowerPC / PPCRegisterInfo.td

diff --git a/lib/Target/PowerPC/PPCRegisterInfo.td b/lib/Target/PowerPC/PPCRegisterInfo.td
index 28c590cc790d2f6d0a4ad8d7cd83d48ae274bf91..57a25f5143fa843c91b1526bb2bb8ead4b9d7eb7 100644 (file)
--- a/lib/Target/PowerPC/PPCRegisterInfo.td
+++ b/lib/Target/PowerPC/PPCRegisterInfo.td
@@ -26,8 +26,8 @@ class PPCReg<string n> : Register<n> {
 // We identify all our registers with a 5-bit ID, for consistency's sake.
 
 // GPR - One of the 32 32-bit general-purpose registers
-class GPR<bits<16> num, string n> : PPCReg<n> {
-  let HWEncoding = num;
+class GPR<bits<5> num, string n> : PPCReg<n> {
+  let HWEncoding{4-0} = num;
 }
 
 // GP8 - One of the 32 64-bit general-purpose registers
@@ -38,29 +38,29 @@ class GP8<GPR SubReg, string n> : PPCReg<n> {
 }
 
 // SPR - One of the 32-bit special-purpose registers
-class SPR<bits<16> num, string n> : PPCReg<n> {
-  let HWEncoding = num;
+class SPR<bits<10> num, string n> : PPCReg<n> {
+  let HWEncoding{9-0} = num;
 }
 
 // FPR - One of the 32 64-bit floating-point registers
-class FPR<bits<16> num, string n> : PPCReg<n> {
-  let HWEncoding = num;
+class FPR<bits<5> num, string n> : PPCReg<n> {
+  let HWEncoding{4-0} = num;
 }
 
 // VR - One of the 32 128-bit vector registers
-class VR<bits<16> num, string n> : PPCReg<n> {
-  let HWEncoding = num;
+class VR<bits<5> num, string n> : PPCReg<n> {
+  let HWEncoding{4-0} = num;
 }
 
 // CR - One of the 8 4-bit condition registers
-class CR<bits<16> num, string n, list<Register> subregs> : PPCReg<n> {
-  let HWEncoding = num;
+class CR<bits<3> num, string n, list<Register> subregs> : PPCReg<n> {
+  let HWEncoding{2-0} = num;
   let SubRegs = subregs;
 }
 
 // CRBIT - One of the 32 1-bit condition register fields
-class CRBIT<bits<16> num, string n> : PPCReg<n> {
-  let HWEncoding = num;
+class CRBIT<bits<5> num, string n> : PPCReg<n> {
+  let HWEncoding{4-0} = num;
 }
 
 // General-purpose registers
@@ -87,8 +87,8 @@ foreach Index = 0-31 in {
 }
 
 // The reprsentation of r0 when treated as the constant 0.
-def ZERO  : GPR<0, "r0">;
-def ZERO8 : GP8<ZERO, "r0">;
+def ZERO  : GPR<0, "0">;
+def ZERO8 : GP8<ZERO, "0">;
 
 // Representations of the frame pointer used by ISD::FRAMEADDR.
 def FP   : GPR<0 /* arbitrary */, "**FRAME POINTER**">;
@@ -172,11 +172,11 @@ def RM: SPR<512, "**ROUNDING MODE**">;
 // then nonvolatiles in reverse order since stmw/lmw save from rN to r31
 def GPRC : RegisterClass<"PPC", [i32], 32, (add (sequence "R%u", 2, 12),
                                                 (sequence "R%u", 30, 13),
-                                                R31, R0, R1, LR, FP)>;
+                                                R31, R0, R1, FP)>;
 
 def G8RC : RegisterClass<"PPC", [i64], 64, (add (sequence "X%u", 2, 12),
                                                 (sequence "X%u", 30, 14),
-                                                X31, X13, X0, X1, LR8, FP8)>;
+                                                X31, X13, X0, X1, FP8)>;
 
 // For some instructions r0 is special (representing the value 0 instead of
 // the value in the r0 register), and we use these register subclasses to