Make LABEL a builtin opcode.

[oota-llvm.git] / lib / Target / PowerPC / PPCRegisterInfo.td

diff --git a/lib/Target/PowerPC/PPCRegisterInfo.td b/lib/Target/PowerPC/PPCRegisterInfo.td
index 4f56cf74e54ff0c90971854e79b78f323e5ff1bd..1950d073169b2a9805f05f018b47e6cd85280072 100644 (file)
--- a/lib/Target/PowerPC/PPCRegisterInfo.td
+++ b/lib/Target/PowerPC/PPCRegisterInfo.td
@@ -195,8 +195,13 @@ def CR7 : CR<7, "cr7">, DwarfRegNum<75>;
 
 // Link register
 def LR  : SPR<8, "lr">, DwarfRegNum<65>;
+//let Aliases = [LR] in
+def LR8 : SPR<8, "lr">, DwarfRegNum<65>;
+
 // Count register
-def CTR : SPR<9, "ctr">, DwarfRegNum<66>;
+def CTR  : SPR<9, "ctr">, DwarfRegNum<66>;
+def CTR8 : SPR<9, "ctr">, DwarfRegNum<66>;
+
 // VRsave register
 def VRSAVE: SPR<256, "VRsave">, DwarfRegNum<107>;
 
@@ -204,22 +209,32 @@ def VRSAVE: SPR<256, "VRsave">, DwarfRegNum<107>;
 // Allocate volatiles first
 // then nonvolatiles in reverse order since stmw/lmw save from rN to r31
 def GPRC : RegisterClass<"PPC", [i32], 32,
-     [R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12,
+     [R3, R4, R5, R6, R7, R8, R9, R10, R11, R12,
       R30, R29, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17,
-      R16, R15, R14, R13, R31, R0, R1, LR]>
+      R16, R15, R14, R2, R13, R31, R0, R1, LR]>
 {
   let MethodProtos = [{
-    iterator allocation_order_begin(MachineFunction &MF) const;
-    iterator allocation_order_end(MachineFunction &MF) const;
+    iterator allocation_order_begin(const MachineFunction &MF) const;
+    iterator allocation_order_end(const MachineFunction &MF) const;
   }];
   let MethodBodies = [{
     GPRCClass::iterator
-    GPRCClass::allocation_order_begin(MachineFunction &MF) const {
-      return begin() + ((TargetAIX == PPCTarget) ? 1 : 0);
+    GPRCClass::allocation_order_begin(const MachineFunction &MF) const {
+      return begin();
     }
     GPRCClass::iterator
-    GPRCClass::allocation_order_end(MachineFunction &MF) const {
-      if (hasFP(MF))
+    GPRCClass::allocation_order_end(const MachineFunction &MF) const {
+      // In Linux, r2 is reserved for the OS.
+      if (!MF.getTarget().getSubtarget<PPCSubtarget>().isDarwin())
+        return end()-6;
+
+      // On PPC64, r13 is the thread pointer.  Never allocate this register.
+      // Note that this is overconservative, as it also prevents allocation of
+      // R31 when the FP is not needed.
+      if (MF.getTarget().getSubtarget<PPCSubtarget>().isPPC64())
+        return end()-5;  // don't allocate R13, R31, R0, R1, LR
+        
+      if (needsFP(MF))
         return end()-4;  // don't allocate R31, R0, R1, LR
       else
         return end()-3;  // don't allocate R0, R1, LR
@@ -229,23 +244,23 @@ def GPRC : RegisterClass<"PPC", [i32], 32,
 def G8RC : RegisterClass<"PPC", [i64], 64,
      [X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12,
       X30, X29, X28, X27, X26, X25, X24, X23, X22, X21, X20, X19, X18, X17,
-      X16, X15, X14, X13, X31, X0, X1]>
+      X16, X15, X14, X31, X13, X0, X1, LR8]>
 {
   let MethodProtos = [{
-    iterator allocation_order_begin(MachineFunction &MF) const;
-    iterator allocation_order_end(MachineFunction &MF) const;
+    iterator allocation_order_begin(const MachineFunction &MF) const;
+    iterator allocation_order_end(const MachineFunction &MF) const;
   }];
   let MethodBodies = [{
     G8RCClass::iterator
-    G8RCClass::allocation_order_begin(MachineFunction &MF) const {
-      return begin() + ((TargetAIX == PPCTarget) ? 1 : 0);
+    G8RCClass::allocation_order_begin(const MachineFunction &MF) const {
+      return begin();
     }
     G8RCClass::iterator
-    G8RCClass::allocation_order_end(MachineFunction &MF) const {
-      if (hasFP(MF))
-        return end()-3;
+    G8RCClass::allocation_order_end(const MachineFunction &MF) const {
+      if (needsFP(MF))
+        return end()-5;
       else
-        return end()-2;
+        return end()-4;
     }
   }];
 }
@@ -260,7 +275,7 @@ def F4RC : RegisterClass<"PPC", [f32], 32, [F0, F1, F2, F3, F4, F5, F6, F7,
   F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
 
 def VRRC : RegisterClass<"PPC", [v16i8,v8i16,v4i32,v4f32], 128,
- [V0, V1, V2, V3, V4, V5,
+ [V2, V3, V4, V5, V0, V1, 
   V6, V7, V8, V9, V10, V11, V12, V13, V14, V15, V16, V17, V18, V19, V20, V21,
   V22, V23, V24, V25, V26, V27, V28, V29, V30, V31]>;