-//===- PPC32RegisterInfo.cpp - PowerPC32 Register Information ---*- C++ -*-===//
+//===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
//
//===----------------------------------------------------------------------===//
//
-// This file contains the PowerPC32 implementation of the MRegisterInfo class.
+// This file contains the PowerPC implementation of the MRegisterInfo class.
//
//===----------------------------------------------------------------------===//
#include <iostream>
using namespace llvm;
-PPC32RegisterInfo::PPC32RegisterInfo()
+PPCRegisterInfo::PPCRegisterInfo()
: PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP) {
ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
}
void
-PPC32RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI,
- unsigned SrcReg, int FrameIdx,
- const TargetRegisterClass *RC) const {
+PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI,
+ unsigned SrcReg, int FrameIdx,
+ const TargetRegisterClass *RC) const {
if (SrcReg == PPC::LR) {
BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11);
addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx);
}
void
-PPC32RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
+PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, int FrameIdx,
const TargetRegisterClass *RC) const {
}
}
-void PPC32RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI,
- unsigned DestReg, unsigned SrcReg,
- const TargetRegisterClass *RC) const {
+void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI,
+ unsigned DestReg, unsigned SrcReg,
+ const TargetRegisterClass *RC) const {
MachineInstr *I;
if (RC == PPC32::GPRCRegisterClass) {
}
}
-unsigned PPC32RegisterInfo::isLoadFromStackSlot(MachineInstr *MI,
- int &FrameIndex) const {
+unsigned PPCRegisterInfo::isLoadFromStackSlot(MachineInstr *MI,
+ int &FrameIndex) const {
switch (MI->getOpcode()) {
default: break;
case PPC::LWZ:
/// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
/// copy instructions, turning them into load/store instructions.
-MachineInstr *PPC32RegisterInfo::foldMemoryOperand(MachineInstr *MI,
- unsigned OpNum,
- int FrameIndex) const {
+MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI,
+ unsigned OpNum,
+ int FrameIndex) const {
// Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
// it takes more than one instruction to store it.
unsigned Opc = MI->getOpcode();
return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
}
-void PPC32RegisterInfo::
+void PPCRegisterInfo::
eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const {
if (hasFP(MF)) {
}
void
-PPC32RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
+PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
unsigned i = 0;
MachineInstr &MI = *II;
MachineBasicBlock &MBB = *MI.getParent();
}
-void PPC32RegisterInfo::emitPrologue(MachineFunction &MF) const {
+void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
MachineBasicBlock::iterator MBBI = MBB.begin();
MachineFrameInfo *MFI = MF.getFrameInfo();
}
}
-void PPC32RegisterInfo::emitEpilogue(MachineFunction &MF,
- MachineBasicBlock &MBB) const {
+void PPCRegisterInfo::emitEpilogue(MachineFunction &MF,
+ MachineBasicBlock &MBB) const {
const MachineFrameInfo *MFI = MF.getFrameInfo();
MachineBasicBlock::iterator MBBI = prior(MBB.end());
MachineInstr *MI;