-//===- PowerPCInstrInfo.td - The PowerPC Instruction Set -----*- tablegen -*-=//
+//===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
//
//===----------------------------------------------------------------------===//
-include "PowerPCInstrFormats.td"
-
-//===----------------------------------------------------------------------===//
-// Selection DAG Type Constraint definitions.
-//
-// Note that the semantics of these constraints are hard coded into tblgen. To
-// modify or add constraints, you have to hack tblgen.
-//
-
-class SDTypeConstraint<int opnum> {
- int OperandNum = opnum;
-}
-
-// SDTCisVT - The specified operand has exactly this VT.
-class SDTCisVT <int OpNum, ValueType vt> : SDTypeConstraint<OpNum> {
- ValueType VT = vt;
-}
-
-// SDTCisInt - The specified operand is has integer type.
-class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>;
-
-// SDTCisFP - The specified operand is has floating point type.
-class SDTCisFP <int OpNum> : SDTypeConstraint<OpNum>;
-
-// SDTCisSameAs - The two specified operands have identical types.
-class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
- int OtherOperandNum = OtherOp;
-}
-
-// SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is
-// smaller than the 'Other' operand.
-class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
- int OtherOperandNum = OtherOp;
-}
-
-//===----------------------------------------------------------------------===//
-// Selection DAG Type Profile definitions.
-//
-// These use the constraints defined above to describe the type requirements of
-// the various nodes. These are not hard coded into tblgen, allowing targets to
-// add their own if needed.
-//
-
-// SDTypeProfile - This profile describes the type requirements of a Selection
-// DAG node.
-class SDTypeProfile<int numresults, int numoperands,
- list<SDTypeConstraint> constraints> {
- int NumResults = numresults;
- int NumOperands = numoperands;
- list<SDTypeConstraint> Constraints = constraints;
-}
-
-// Builtin profiles.
-def SDTImm : SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'.
-def SDTVT : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'
-def SDTBinOp : SDTypeProfile<1, 2, [ // add, mul, etc.
- SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
-]>;
-def SDTIntBinOp : SDTypeProfile<1, 2, [ // and, or, xor, udiv, etc.
- SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>
-]>;
-def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz
- SDTCisSameAs<0, 1>, SDTCisInt<0>
-]>;
-def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg
- SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>,
- SDTCisVTSmallerThanOp<2, 1>
-]>;
+include "PPCInstrFormats.td"
//===----------------------------------------------------------------------===//
-// Selection DAG Node definitions.
-//
-class SDNode<string opcode, SDTypeProfile typeprof, string sdclass = "SDNode"> {
- string Opcode = opcode;
- string SDClass = sdclass;
- SDTypeProfile TypeProfile = typeprof;
-}
-
-def set;
-def node;
-
-def imm : SDNode<"ISD::Constant" , SDTImm , "ConstantSDNode">;
-def vt : SDNode<"ISD::VALUETYPE" , SDTVT , "VTSDNode">;
-def and : SDNode<"ISD::AND" , SDTIntBinOp>;
-def or : SDNode<"ISD::OR" , SDTIntBinOp>;
-def xor : SDNode<"ISD::XOR" , SDTIntBinOp>;
-def add : SDNode<"ISD::ADD" , SDTBinOp>;
-def sub : SDNode<"ISD::SUB" , SDTBinOp>;
-def mul : SDNode<"ISD::MUL" , SDTBinOp>;
-def sdiv : SDNode<"ISD::SDIV" , SDTBinOp>;
-def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>;
-def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp>;
-def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp>;
-def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
-def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;
-
-//===----------------------------------------------------------------------===//
-// Selection DAG Node Transformation Functions.
-//
-// This mechanism allows targets to manipulate nodes in the output DAG once a
-// match has been formed. This is typically used to manipulate immediate
-// values.
-//
-class SDNodeXForm<SDNode opc, code xformFunction> {
- SDNode Opcode = opc;
- code XFormFunction = xformFunction;
-}
-
-def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>;
-
-
-//===----------------------------------------------------------------------===//
-// Selection DAG Pattern Fragments.
-//
-// Pattern fragments are reusable chunks of dags that match specific things.
-// They can take arguments and have C++ predicates that control whether they
-// match. They are intended to make the patterns for common instructions more
-// compact and readable.
+// PowerPC specific transformation functions and pattern fragments.
//
-/// PatFrag - Represents a pattern fragment. This can match something on the
-/// DAG, frame a single node to multiply nested other fragments.
-///
-class PatFrag<dag ops, dag frag, code pred = [{}],
- SDNodeXForm xform = NOOP_SDNodeXForm> {
- dag Operands = ops;
- dag Fragment = frag;
- code Predicate = pred;
- SDNodeXForm OperandTransform = xform;
-}
-
-// PatLeaf's are pattern fragments that have no operands. This is just a helper
-// to define immediates and other common things concisely.
-class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm>
- : PatFrag<(ops), frag, pred, xform>;
-
-// Leaf fragments.
-
-def immAllOnes : PatLeaf<(imm), [{ return N->isAllOnesValue(); }]>;
-def immZero : PatLeaf<(imm), [{ return N->isNullValue(); }]>;
-
-def vtInt : PatLeaf<(vt), [{ return MVT::isInteger(N->getVT()); }]>;
-def vtFP : PatLeaf<(vt), [{ return MVT::isFloatingPoint(N->getVT()); }]>;
-
-// Other helper fragments.
-
-def not : PatFrag<(ops node:$in), (xor node:$in, immAllOnes)>;
-def ineg : PatFrag<(ops node:$in), (sub immZero, node:$in)>;
-
-//===----------------------------------------------------------------------===//
-// Selection DAG Pattern Support.
-//
-// Patterns are what are actually matched against the target-flavored
-// instruction selection DAG. Instructions defined by the target implicitly
-// define patterns in most cases, but patterns can also be explicitly added when
-// an operation is defined by a sequence of instructions (e.g. loading a large
-// immediate value on RISC targets that do not support immediates as large as
-// their GPRs).
-//
+def SHL32 : SDNodeXForm<imm, [{
+ // Transformation function: 31 - imm
+ return getI32Imm(31 - N->getValue());
+}]>;
-class Pattern<dag patternToMatch, list<dag> resultInstrs> {
- dag PatternToMatch = patternToMatch;
- list<dag> ResultInstrs = resultInstrs;
-}
+def SHL64 : SDNodeXForm<imm, [{
+ // Transformation function: 63 - imm
+ return getI32Imm(63 - N->getValue());
+}]>;
-// Pat - A simple (but common) form of a pattern, which produces a simple result
-// not needing a full list.
-class Pat<dag pattern, dag result> : Pattern<pattern, [result]>;
+def SRL32 : SDNodeXForm<imm, [{
+ // Transformation function: 32 - imm
+ return N->getValue() ? getI32Imm(32 - N->getValue()) : getI32Imm(0);
+}]>;
+def SRL64 : SDNodeXForm<imm, [{
+ // Transformation function: 64 - imm
+ return N->getValue() ? getI32Imm(64 - N->getValue()) : getI32Imm(0);
+}]>;
-//===----------------------------------------------------------------------===//
-// PowerPC specific transformation functions and pattern fragments.
-//
def LO16 : SDNodeXForm<imm, [{
// Transformation function: get the low 16 bits.
return getI32Imm((unsigned short)N->getValue());
return getI32Imm((unsigned)N->getValue() >> 16);
}]>;
+def HA16 : SDNodeXForm<imm, [{
+ // Transformation function: shift the immediate value down into the low bits.
+ signed int Val = N->getValue();
+ return getI32Imm((Val - (signed short)Val) >> 16);
+}]>;
+
+
def immSExt16 : PatLeaf<(imm), [{
// immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
// field. Used by instructions like 'addi'.
def u16imm : Operand<i32> {
let PrintMethod = "printU16ImmOperand";
}
+def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing.
+ let PrintMethod = "printS16X4ImmOperand";
+}
def target : Operand<i32> {
let PrintMethod = "printBranchOperand";
}
def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt), "; ADJCALLSTACKUP">;
}
def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC">;
-def IMPLICIT_DEF_FP : Pseudo<(ops FPRC:$rD), "; %rD = IMPLICIT_DEF_FP">;
+def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "; %rD = IMPLICIT_DEF_F8">;
+def IMPLICIT_DEF_F4 : Pseudo<(ops F4RC:$rD), "; %rD = IMPLICIT_DEF_F4">;
// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
// scheduler into a branch sequence.
let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
def SELECT_CC_Int : Pseudo<(ops GPRC:$dst, CRRC:$cond, GPRC:$T, GPRC:$F,
i32imm:$BROPC), "; SELECT_CC PSEUDO!">;
- def SELECT_CC_FP : Pseudo<(ops FPRC:$dst, CRRC:$cond, FPRC:$T, FPRC:$F,
+ def SELECT_CC_F4 : Pseudo<(ops F4RC:$dst, CRRC:$cond, F4RC:$T, F4RC:$F,
+ i32imm:$BROPC), "; SELECT_CC PSEUDO!">;
+ def SELECT_CC_F8 : Pseudo<(ops F8RC:$dst, CRRC:$cond, F8RC:$T, F8RC:$F,
i32imm:$BROPC), "; SELECT_CC PSEUDO!">;
}
let isTerminator = 1 in {
let isReturn = 1 in
- def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr">;
- def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr">;
+ def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr", BrB>;
+ def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr", BrB>;
}
let Defs = [LR] in
def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm:$opc,
target:$true, target:$false),
"; COND_BRANCH">;
- def B : IForm<18, 0, 0, (ops target:$func), "b $func">;
-//def BA : IForm<18, 1, 0, (ops target:$func), "ba $func">;
- def BL : IForm<18, 0, 1, (ops target:$func), "bl $func">;
-//def BLA : IForm<18, 1, 1, (ops target:$func), "bla $func">;
+ def B : IForm<18, 0, 0, (ops target:$func), "b $func", BrB>;
+//def BA : IForm<18, 1, 0, (ops target:$func), "ba $func", BrB>;
+ def BL : IForm<18, 0, 1, (ops target:$func), "bl $func", BrB>;
+//def BLA : IForm<18, 1, 1, (ops target:$func), "bla $func", BrB>;
// FIXME: 4*CR# needs to be added to the BI field!
// This will only work for CR0 as it stands now
def BLT : BForm<16, 0, 0, 12, 0, (ops CRRC:$crS, target:$block),
- "blt $crS, $block">;
+ "blt $crS, $block", BrB>;
def BLE : BForm<16, 0, 0, 4, 1, (ops CRRC:$crS, target:$block),
- "ble $crS, $block">;
+ "ble $crS, $block", BrB>;
def BEQ : BForm<16, 0, 0, 12, 2, (ops CRRC:$crS, target:$block),
- "beq $crS, $block">;
+ "beq $crS, $block", BrB>;
def BGE : BForm<16, 0, 0, 4, 0, (ops CRRC:$crS, target:$block),
- "bge $crS, $block">;
+ "bge $crS, $block", BrB>;
def BGT : BForm<16, 0, 0, 12, 1, (ops CRRC:$crS, target:$block),
- "bgt $crS, $block">;
+ "bgt $crS, $block", BrB>;
def BNE : BForm<16, 0, 0, 4, 2, (ops CRRC:$crS, target:$block),
- "bne $crS, $block">;
+ "bne $crS, $block", BrB>;
}
let isCall = 1,
LR,CTR,
CR0,CR1,CR5,CR6,CR7] in {
// Convenient aliases for call instructions
- def CALLpcrel : IForm<18, 0, 1, (ops target:$func, variable_ops), "bl $func">;
+ def CALLpcrel : IForm<18, 0, 1, (ops target:$func, variable_ops),
+ "bl $func", BrB>;
def CALLindirect : XLForm_2_ext<19, 528, 20, 0, 1,
- (ops variable_ops), "bctrl">;
+ (ops variable_ops), "bctrl", BrB>;
}
// D-Form instructions. Most instructions that perform an operation on a
//
let isLoad = 1 in {
def LBZ : DForm_1<34, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
- "lbz $rD, $disp($rA)">;
+ "lbz $rD, $disp($rA)", LdStGeneral>;
def LHA : DForm_1<42, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
- "lha $rD, $disp($rA)">;
+ "lha $rD, $disp($rA)", LdStLHA>;
def LHZ : DForm_1<40, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
- "lhz $rD, $disp($rA)">;
+ "lhz $rD, $disp($rA)", LdStGeneral>;
def LMW : DForm_1<46, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
- "lmw $rD, $disp($rA)">;
+ "lmw $rD, $disp($rA)", LdStLMW>;
def LWZ : DForm_1<32, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
- "lwz $rD, $disp($rA)">;
+ "lwz $rD, $disp($rA)", LdStGeneral>;
def LWZU : DForm_1<35, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
- "lwzu $rD, $disp($rA)">;
+ "lwzu $rD, $disp($rA)", LdStGeneral>;
}
def ADDI : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
- "addi $rD, $rA, $imm",
+ "addi $rD, $rA, $imm", IntGeneral,
[(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
def ADDIC : DForm_2<12, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
- "addic $rD, $rA, $imm",
+ "addic $rD, $rA, $imm", IntGeneral,
[]>;
def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
- "addic. $rD, $rA, $imm",
+ "addic. $rD, $rA, $imm", IntGeneral,
[]>;
def ADDIS : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$imm),
- "addis $rD, $rA, $imm",
+ "addis $rD, $rA, $imm", IntGeneral,
[(set GPRC:$rD, (add GPRC:$rA, imm16Shifted:$imm))]>;
def LA : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym),
- "la $rD, $sym($rA)",
+ "la $rD, $sym($rA)", IntGeneral,
[]>;
def MULLI : DForm_2< 7, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
- "mulli $rD, $rA, $imm",
+ "mulli $rD, $rA, $imm", IntMulLI,
[(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
def SUBFIC : DForm_2< 8, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
- "subfic $rD, $rA, $imm",
- []>;
+ "subfic $rD, $rA, $imm", IntGeneral,
+ [(set GPRC:$rD, (sub immSExt16:$imm, GPRC:$rA))]>;
def LI : DForm_2_r0<14, (ops GPRC:$rD, s16imm:$imm),
- "li $rD, $imm",
+ "li $rD, $imm", IntGeneral,
[(set GPRC:$rD, immSExt16:$imm)]>;
def LIS : DForm_2_r0<15, (ops GPRC:$rD, symbolHi:$imm),
- "lis $rD, $imm",
+ "lis $rD, $imm", IntGeneral,
[(set GPRC:$rD, imm16Shifted:$imm)]>;
let isStore = 1 in {
def STMW : DForm_3<47, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
- "stmw $rS, $disp($rA)">;
+ "stmw $rS, $disp($rA)", LdStLMW>;
def STB : DForm_3<38, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
- "stb $rS, $disp($rA)">;
+ "stb $rS, $disp($rA)", LdStGeneral>;
def STH : DForm_3<44, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
- "sth $rS, $disp($rA)">;
+ "sth $rS, $disp($rA)", LdStGeneral>;
def STW : DForm_3<36, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
- "stw $rS, $disp($rA)">;
+ "stw $rS, $disp($rA)", LdStGeneral>;
def STWU : DForm_3<37, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
- "stwu $rS, $disp($rA)">;
+ "stwu $rS, $disp($rA)", LdStGeneral>;
}
def ANDIo : DForm_4<28, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
- "andi. $dst, $src1, $src2",
+ "andi. $dst, $src1, $src2", IntGeneral,
[]>, isDOT;
def ANDISo : DForm_4<29, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
- "andis. $dst, $src1, $src2",
+ "andis. $dst, $src1, $src2", IntGeneral,
[]>, isDOT;
def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
- "ori $dst, $src1, $src2",
+ "ori $dst, $src1, $src2", IntGeneral,
[(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
def ORIS : DForm_4<25, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
- "oris $dst, $src1, $src2",
+ "oris $dst, $src1, $src2", IntGeneral,
[(set GPRC:$dst, (or GPRC:$src1, imm16Shifted:$src2))]>;
def XORI : DForm_4<26, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
- "xori $dst, $src1, $src2",
+ "xori $dst, $src1, $src2", IntGeneral,
[(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
def XORIS : DForm_4<27, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
- "xoris $dst, $src1, $src2",
+ "xoris $dst, $src1, $src2", IntGeneral,
[(set GPRC:$dst, (xor GPRC:$src1, imm16Shifted:$src2))]>;
-def NOP : DForm_4_zero<24, (ops), "nop">;
+def NOP : DForm_4_zero<24, (ops), "nop", IntGeneral>;
def CMPI : DForm_5<11, (ops CRRC:$crD, i1imm:$L, GPRC:$rA, s16imm:$imm),
- "cmpi $crD, $L, $rA, $imm">;
+ "cmpi $crD, $L, $rA, $imm", IntCompare>;
def CMPWI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
- "cmpwi $crD, $rA, $imm">;
+ "cmpwi $crD, $rA, $imm", IntCompare>;
def CMPDI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
- "cmpdi $crD, $rA, $imm">, isPPC64;
+ "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64;
def CMPLI : DForm_6<10, (ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2),
- "cmpli $dst, $size, $src1, $src2">;
+ "cmpli $dst, $size, $src1, $src2", IntCompare>;
def CMPLWI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
- "cmplwi $dst, $src1, $src2">;
+ "cmplwi $dst, $src1, $src2", IntCompare>;
def CMPLDI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
- "cmpldi $dst, $src1, $src2">, isPPC64;
+ "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64;
let isLoad = 1 in {
-def LFS : DForm_8<48, (ops FPRC:$rD, symbolLo:$disp, GPRC:$rA),
- "lfs $rD, $disp($rA)">;
-def LFD : DForm_8<50, (ops FPRC:$rD, symbolLo:$disp, GPRC:$rA),
- "lfd $rD, $disp($rA)">;
+def LFS : DForm_8<48, (ops F4RC:$rD, symbolLo:$disp, GPRC:$rA),
+ "lfs $rD, $disp($rA)", LdStLFDU>;
+def LFD : DForm_8<50, (ops F8RC:$rD, symbolLo:$disp, GPRC:$rA),
+ "lfd $rD, $disp($rA)", LdStLFD>;
}
let isStore = 1 in {
-def STFS : DForm_9<52, (ops FPRC:$rS, symbolLo:$disp, GPRC:$rA),
- "stfs $rS, $disp($rA)">;
-def STFD : DForm_9<54, (ops FPRC:$rS, symbolLo:$disp, GPRC:$rA),
- "stfd $rS, $disp($rA)">;
+def STFS : DForm_9<52, (ops F4RC:$rS, symbolLo:$disp, GPRC:$rA),
+ "stfs $rS, $disp($rA)", LdStUX>;
+def STFD : DForm_9<54, (ops F8RC:$rS, symbolLo:$disp, GPRC:$rA),
+ "stfd $rS, $disp($rA)", LdStUX>;
}
// DS-Form instructions. Load/Store instructions available in PPC-64
//
let isLoad = 1 in {
-def LWA : DSForm_1<58, 2, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
- "lwa $rT, $DS($rA)">, isPPC64;
-def LD : DSForm_2<58, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
- "ld $rT, $DS($rA)">, isPPC64;
+def LWA : DSForm_1<58, 2, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
+ "lwa $rT, $DS($rA)", LdStLWA>, isPPC64;
+def LD : DSForm_2<58, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
+ "ld $rT, $DS($rA)", LdStLD>, isPPC64;
}
let isStore = 1 in {
-def STD : DSForm_2<62, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
- "std $rT, $DS($rA)">, isPPC64;
-def STDU : DSForm_2<62, 1, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
- "stdu $rT, $DS($rA)">, isPPC64;
+def STD : DSForm_2<62, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
+ "std $rT, $DS($rA)", LdStSTD>, isPPC64;
+def STDU : DSForm_2<62, 1, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
+ "stdu $rT, $DS($rA)", LdStSTD>, isPPC64;
}
// X-Form instructions. Most instructions that perform an operation on a
//
let isLoad = 1 in {
def LBZX : XForm_1<31, 87, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
- "lbzx $dst, $base, $index">;
+ "lbzx $dst, $base, $index", LdStGeneral>;
def LHAX : XForm_1<31, 343, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
- "lhax $dst, $base, $index">;
+ "lhax $dst, $base, $index", LdStLHA>;
def LHZX : XForm_1<31, 279, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
- "lhzx $dst, $base, $index">;
+ "lhzx $dst, $base, $index", LdStGeneral>;
def LWAX : XForm_1<31, 341, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
- "lwax $dst, $base, $index">, isPPC64;
+ "lwax $dst, $base, $index", LdStLHA>, isPPC64;
def LWZX : XForm_1<31, 23, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
- "lwzx $dst, $base, $index">;
+ "lwzx $dst, $base, $index", LdStGeneral>;
def LDX : XForm_1<31, 21, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
- "ldx $dst, $base, $index">, isPPC64;
+ "ldx $dst, $base, $index", LdStLD>, isPPC64;
}
def NAND : XForm_6<31, 476, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
- "nand $rA, $rS, $rB",
+ "nand $rA, $rS, $rB", IntGeneral,
[(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
def AND : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
- "and $rA, $rS, $rB",
+ "and $rA, $rS, $rB", IntGeneral,
[(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
def ANDo : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
- "and. $rA, $rS, $rB",
+ "and. $rA, $rS, $rB", IntGeneral,
[]>, isDOT;
def ANDC : XForm_6<31, 60, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
- "andc $rA, $rS, $rB",
+ "andc $rA, $rS, $rB", IntGeneral,
[(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
-def OR : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
- "or $rA, $rS, $rB",
+def OR4 : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
+ "or $rA, $rS, $rB", IntGeneral,
[(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
+def OR8 : XForm_6<31, 444, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
+ "or $rA, $rS, $rB", IntGeneral,
+ [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>;
+def OR4To8 : XForm_6<31, 444, (ops G8RC:$rA, GPRC:$rS, GPRC:$rB),
+ "or $rA, $rS, $rB", IntGeneral,
+ []>;
+def OR8To4 : XForm_6<31, 444, (ops GPRC:$rA, G8RC:$rS, G8RC:$rB),
+ "or $rA, $rS, $rB", IntGeneral,
+ []>;
def NOR : XForm_6<31, 124, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
- "nor $rA, $rS, $rB",
+ "nor $rA, $rS, $rB", IntGeneral,
[(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
def ORo : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
- "or. $rA, $rS, $rB",
+ "or. $rA, $rS, $rB", IntGeneral,
[]>, isDOT;
def ORC : XForm_6<31, 412, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
- "orc $rA, $rS, $rB",
+ "orc $rA, $rS, $rB", IntGeneral,
[(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
def EQV : XForm_6<31, 284, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
- "eqv $rA, $rS, $rB",
+ "eqv $rA, $rS, $rB", IntGeneral,
[(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
def XOR : XForm_6<31, 316, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
- "xor $rA, $rS, $rB",
+ "xor $rA, $rS, $rB", IntGeneral,
[(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
-def SLD : XForm_6<31, 27, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
- "sld $rA, $rS, $rB",
- []>, isPPC64;
+def SLD : XForm_6<31, 27, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
+ "sld $rA, $rS, $rB", IntRotateD,
+ [(set G8RC:$rA, (shl G8RC:$rS, G8RC:$rB))]>, isPPC64;
def SLW : XForm_6<31, 24, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
- "slw $rA, $rS, $rB",
- []>;
-def SRD : XForm_6<31, 539, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
- "srd $rA, $rS, $rB",
- []>, isPPC64;
+ "slw $rA, $rS, $rB", IntGeneral,
+ [(set GPRC:$rA, (shl GPRC:$rS, GPRC:$rB))]>;
+def SRD : XForm_6<31, 539, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
+ "srd $rA, $rS, $rB", IntRotateD,
+ [(set G8RC:$rA, (srl G8RC:$rS, G8RC:$rB))]>, isPPC64;
def SRW : XForm_6<31, 536, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
- "srw $rA, $rS, $rB",
- []>;
-def SRAD : XForm_6<31, 794, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
- "srad $rA, $rS, $rB",
- []>, isPPC64;
+ "srw $rA, $rS, $rB", IntGeneral,
+ [(set GPRC:$rA, (srl GPRC:$rS, GPRC:$rB))]>;
+def SRAD : XForm_6<31, 794, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
+ "srad $rA, $rS, $rB", IntRotateD,
+ [(set G8RC:$rA, (sra G8RC:$rS, G8RC:$rB))]>, isPPC64;
def SRAW : XForm_6<31, 792, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
- "sraw $rA, $rS, $rB",
- []>;
+ "sraw $rA, $rS, $rB", IntShift,
+ [(set GPRC:$rA, (sra GPRC:$rS, GPRC:$rB))]>;
let isStore = 1 in {
def STBX : XForm_8<31, 215, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
- "stbx $rS, $rA, $rB">;
+ "stbx $rS, $rA, $rB", LdStGeneral>;
def STHX : XForm_8<31, 407, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
- "sthx $rS, $rA, $rB">;
+ "sthx $rS, $rA, $rB", LdStGeneral>;
def STWX : XForm_8<31, 151, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
- "stwx $rS, $rA, $rB">;
+ "stwx $rS, $rA, $rB", LdStGeneral>;
def STWUX : XForm_8<31, 183, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
- "stwux $rS, $rA, $rB">;
+ "stwux $rS, $rA, $rB", LdStGeneral>;
def STDX : XForm_8<31, 149, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
- "stdx $rS, $rA, $rB">, isPPC64;
+ "stdx $rS, $rA, $rB", LdStSTD>, isPPC64;
def STDUX : XForm_8<31, 181, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
- "stdux $rS, $rA, $rB">, isPPC64;
+ "stdux $rS, $rA, $rB", LdStSTD>, isPPC64;
}
def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
- "srawi $rA, $rS, $SH">;
+ "srawi $rA, $rS, $SH", IntShift,
+ [(set GPRC:$rA, (sra GPRC:$rS, imm:$SH))]>;
def CNTLZW : XForm_11<31, 26, (ops GPRC:$rA, GPRC:$rS),
- "cntlzw $rA, $rS",
+ "cntlzw $rA, $rS", IntGeneral,
[(set GPRC:$rA, (ctlz GPRC:$rS))]>;
def EXTSB : XForm_11<31, 954, (ops GPRC:$rA, GPRC:$rS),
- "extsb $rA, $rS",
+ "extsb $rA, $rS", IntGeneral,
[(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
def EXTSH : XForm_11<31, 922, (ops GPRC:$rA, GPRC:$rS),
- "extsh $rA, $rS",
+ "extsh $rA, $rS", IntGeneral,
[(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
def EXTSW : XForm_11<31, 986, (ops GPRC:$rA, GPRC:$rS),
- "extsw $rA, $rS",
+ "extsw $rA, $rS", IntRotateD,
[]>, isPPC64;
def CMP : XForm_16<31, 0, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
- "cmp $crD, $long, $rA, $rB">;
+ "cmp $crD, $long, $rA, $rB", IntCompare>;
def CMPL : XForm_16<31, 32, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
- "cmpl $crD, $long, $rA, $rB">;
+ "cmpl $crD, $long, $rA, $rB", IntCompare>;
def CMPW : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
- "cmpw $crD, $rA, $rB">;
+ "cmpw $crD, $rA, $rB", IntCompare>;
def CMPD : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
- "cmpd $crD, $rA, $rB">, isPPC64;
+ "cmpd $crD, $rA, $rB", IntCompare>, isPPC64;
def CMPLW : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
- "cmplw $crD, $rA, $rB">;
+ "cmplw $crD, $rA, $rB", IntCompare>;
def CMPLD : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
- "cmpld $crD, $rA, $rB">, isPPC64;
-def FCMPO : XForm_17<63, 32, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
- "fcmpo $crD, $fA, $fB">;
-def FCMPU : XForm_17<63, 0, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
- "fcmpu $crD, $fA, $fB">;
+ "cmpld $crD, $rA, $rB", IntCompare>, isPPC64;
+//def FCMPO : XForm_17<63, 32, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
+// "fcmpo $crD, $fA, $fB", FPCompare>;
+def FCMPUS : XForm_17<63, 0, (ops CRRC:$crD, F4RC:$fA, F4RC:$fB),
+ "fcmpu $crD, $fA, $fB", FPCompare>;
+def FCMPUD : XForm_17<63, 0, (ops CRRC:$crD, F8RC:$fA, F8RC:$fB),
+ "fcmpu $crD, $fA, $fB", FPCompare>;
+
let isLoad = 1 in {
-def LFSX : XForm_25<31, 535, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
- "lfsx $dst, $base, $index">;
-def LFDX : XForm_25<31, 599, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
- "lfdx $dst, $base, $index">;
+def LFSX : XForm_25<31, 535, (ops F4RC:$dst, GPRC:$base, GPRC:$index),
+ "lfsx $dst, $base, $index", LdStLFDU>;
+def LFDX : XForm_25<31, 599, (ops F8RC:$dst, GPRC:$base, GPRC:$index),
+ "lfdx $dst, $base, $index", LdStLFDU>;
}
-def FCFID : XForm_26<63, 846, (ops FPRC:$frD, FPRC:$frB),
- "fcfid $frD, $frB">, isPPC64;
-def FCTIDZ : XForm_26<63, 815, (ops FPRC:$frD, FPRC:$frB),
- "fctidz $frD, $frB">, isPPC64;
-def FCTIWZ : XForm_26<63, 15, (ops FPRC:$frD, FPRC:$frB),
- "fctiwz $frD, $frB">;
-def FABS : XForm_26<63, 264, (ops FPRC:$frD, FPRC:$frB),
- "fabs $frD, $frB">;
-def FMR : XForm_26<63, 72, (ops FPRC:$frD, FPRC:$frB),
- "fmr $frD, $frB">;
-def FNABS : XForm_26<63, 136, (ops FPRC:$frD, FPRC:$frB),
- "fnabs $frD, $frB">;
-def FNEG : XForm_26<63, 40, (ops FPRC:$frD, FPRC:$frB),
- "fneg $frD, $frB">;
-def FRSP : XForm_26<63, 12, (ops FPRC:$frD, FPRC:$frB),
- "frsp $frD, $frB">;
-def FSQRT : XForm_26<63, 22, (ops FPRC:$frD, FPRC:$frB),
- "fsqrt $frD, $frB">;
-def FSQRTS : XForm_26<59, 22, (ops FPRC:$frD, FPRC:$frB),
- "fsqrts $frD, $frB">;
+def FCFID : XForm_26<63, 846, (ops F8RC:$frD, F8RC:$frB),
+ "fcfid $frD, $frB", FPGeneral,
+ []>, isPPC64;
+def FCTIDZ : XForm_26<63, 815, (ops F8RC:$frD, F8RC:$frB),
+ "fctidz $frD, $frB", FPGeneral,
+ []>, isPPC64;
+def FCTIWZ : XForm_26<63, 15, (ops F8RC:$frD, F8RC:$frB),
+ "fctiwz $frD, $frB", FPGeneral,
+ []>;
+def FRSP : XForm_26<63, 12, (ops F4RC:$frD, F8RC:$frB),
+ "frsp $frD, $frB", FPGeneral,
+ [(set F4RC:$frD, (fround F8RC:$frB))]>;
+def FSQRT : XForm_26<63, 22, (ops F8RC:$frD, F8RC:$frB),
+ "fsqrt $frD, $frB", FPSqrt,
+ [(set F8RC:$frD, (fsqrt F8RC:$frB))]>;
+def FSQRTS : XForm_26<59, 22, (ops F4RC:$frD, F4RC:$frB),
+ "fsqrts $frD, $frB", FPSqrt,
+ [(set F4RC:$frD, (fsqrt F4RC:$frB))]>;
+
+/// FMR is split into 3 versions, one for 4/8 byte FP, and one for extending.
+def FMRS : XForm_26<63, 72, (ops F4RC:$frD, F4RC:$frB),
+ "fmr $frD, $frB", FPGeneral,
+ []>; // (set F4RC:$frD, F4RC:$frB)
+def FMRD : XForm_26<63, 72, (ops F8RC:$frD, F8RC:$frB),
+ "fmr $frD, $frB", FPGeneral,
+ []>; // (set F8RC:$frD, F8RC:$frB)
+def FMRSD : XForm_26<63, 72, (ops F8RC:$frD, F4RC:$frB),
+ "fmr $frD, $frB", FPGeneral,
+ [(set F8RC:$frD, (fextend F4RC:$frB))]>;
+
+// These are artificially split into two different forms, for 4/8 byte FP.
+def FABSS : XForm_26<63, 264, (ops F4RC:$frD, F4RC:$frB),
+ "fabs $frD, $frB", FPGeneral,
+ [(set F4RC:$frD, (fabs F4RC:$frB))]>;
+def FABSD : XForm_26<63, 264, (ops F8RC:$frD, F8RC:$frB),
+ "fabs $frD, $frB", FPGeneral,
+ [(set F8RC:$frD, (fabs F8RC:$frB))]>;
+def FNABSS : XForm_26<63, 136, (ops F4RC:$frD, F4RC:$frB),
+ "fnabs $frD, $frB", FPGeneral,
+ [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>;
+def FNABSD : XForm_26<63, 136, (ops F8RC:$frD, F8RC:$frB),
+ "fnabs $frD, $frB", FPGeneral,
+ [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>;
+def FNEGS : XForm_26<63, 40, (ops F4RC:$frD, F4RC:$frB),
+ "fneg $frD, $frB", FPGeneral,
+ [(set F4RC:$frD, (fneg F4RC:$frB))]>;
+def FNEGD : XForm_26<63, 40, (ops F8RC:$frD, F8RC:$frB),
+ "fneg $frD, $frB", FPGeneral,
+ [(set F8RC:$frD, (fneg F8RC:$frB))]>;
+
let isStore = 1 in {
-def STFSX : XForm_28<31, 663, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
- "stfsx $frS, $rA, $rB">;
-def STFDX : XForm_28<31, 727, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
- "stfdx $frS, $rA, $rB">;
+def STFSX : XForm_28<31, 663, (ops F4RC:$frS, GPRC:$rA, GPRC:$rB),
+ "stfsx $frS, $rA, $rB", LdStUX>;
+def STFDX : XForm_28<31, 727, (ops F8RC:$frS, GPRC:$rA, GPRC:$rB),
+ "stfdx $frS, $rA, $rB", LdStUX>;
}
// XL-Form instructions. condition register logical ops.
//
def MCRF : XLForm_3<19, 0, (ops CRRC:$BF, CRRC:$BFA),
- "mcrf $BF, $BFA">;
+ "mcrf $BF, $BFA", BrMCR>;
// XFX-Form instructions. Instructions that deal with SPRs
//
// Note that although LR should be listed as `8' and CTR as `9' in the SPR
// field, the manual lists the groups of bits as [5-9] = 0, [0-4] = 8 or 9
// which means the SPR value needs to be multiplied by a factor of 32.
-def MFCTR : XFXForm_1_ext<31, 339, 288, (ops GPRC:$rT), "mfctr $rT">;
-def MFLR : XFXForm_1_ext<31, 339, 256, (ops GPRC:$rT), "mflr $rT">;
-def MFCR : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT">;
+def MFCTR : XFXForm_1_ext<31, 339, 288, (ops GPRC:$rT), "mfctr $rT", SprMFSPR>;
+def MFLR : XFXForm_1_ext<31, 339, 256, (ops GPRC:$rT), "mflr $rT", SprMFSPR>;
+def MFCR : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT", SprMFCR>;
def MTCRF : XFXForm_5<31, 144, (ops crbitm:$FXM, GPRC:$rS),
- "mtcrf $FXM, $rS">;
+ "mtcrf $FXM, $rS", BrMCRX>;
def MFOCRF : XFXForm_5a<31, 19, (ops GPRC:$rT, crbitm:$FXM),
- "mfcr $rT, $FXM">;
-def MTCTR : XFXForm_7_ext<31, 467, 288, (ops GPRC:$rS), "mtctr $rS">;
-def MTLR : XFXForm_7_ext<31, 467, 256, (ops GPRC:$rS), "mtlr $rS">;
+ "mfcr $rT, $FXM", SprMFCR>;
+def MTCTR : XFXForm_7_ext<31, 467, 288, (ops GPRC:$rS), "mtctr $rS", SprMTSPR>;
+def MTLR : XFXForm_7_ext<31, 467, 256, (ops GPRC:$rS), "mtlr $rS", SprMTSPR>;
// XS-Form instructions. Just 'sradi'
//
def SRADI : XSForm_1<31, 413, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH),
- "sradi $rA, $rS, $SH">, isPPC64;
+ "sradi $rA, $rS, $SH", IntRotateD>, isPPC64;
// XO-Form instructions. Arithmetic instructions that can set overflow bit
//
-def ADD : XOForm_1<31, 266, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
- "add $rT, $rA, $rB",
+def ADD4 : XOForm_1<31, 266, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
+ "add $rT, $rA, $rB", IntGeneral,
[(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
+def ADD8 : XOForm_1<31, 266, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
+ "add $rT, $rA, $rB", IntGeneral,
+ [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>;
def ADDC : XOForm_1<31, 10, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
- "addc $rT, $rA, $rB",
+ "addc $rT, $rA, $rB", IntGeneral,
[]>;
def ADDE : XOForm_1<31, 138, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
- "adde $rT, $rA, $rB",
+ "adde $rT, $rA, $rB", IntGeneral,
[]>;
def DIVD : XOForm_1<31, 489, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
- "divd $rT, $rA, $rB",
+ "divd $rT, $rA, $rB", IntDivD,
[]>, isPPC64;
def DIVDU : XOForm_1<31, 457, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
- "divdu $rT, $rA, $rB",
+ "divdu $rT, $rA, $rB", IntDivD,
[]>, isPPC64;
def DIVW : XOForm_1<31, 491, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
- "divw $rT, $rA, $rB",
+ "divw $rT, $rA, $rB", IntDivW,
[(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>;
def DIVWU : XOForm_1<31, 459, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
- "divwu $rT, $rA, $rB",
+ "divwu $rT, $rA, $rB", IntDivW,
[(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>;
def MULHW : XOForm_1<31, 75, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
- "mulhw $rT, $rA, $rB",
+ "mulhw $rT, $rA, $rB", IntMulHW,
[(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
def MULHWU : XOForm_1<31, 11, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
- "mulhwu $rT, $rA, $rB",
+ "mulhwu $rT, $rA, $rB", IntMulHWU,
[(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
def MULLD : XOForm_1<31, 233, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
- "mulld $rT, $rA, $rB",
+ "mulld $rT, $rA, $rB", IntMulHD,
[]>, isPPC64;
def MULLW : XOForm_1<31, 235, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
- "mullw $rT, $rA, $rB",
+ "mullw $rT, $rA, $rB", IntMulHW,
[(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
def SUBF : XOForm_1<31, 40, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
- "subf $rT, $rA, $rB",
+ "subf $rT, $rA, $rB", IntGeneral,
[(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
def SUBFC : XOForm_1<31, 8, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
- "subfc $rT, $rA, $rB",
+ "subfc $rT, $rA, $rB", IntGeneral,
[]>;
def SUBFE : XOForm_1<31, 136, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
- "subfe $rT, $rA, $rB",
+ "subfe $rT, $rA, $rB", IntGeneral,
[]>;
def ADDME : XOForm_3<31, 234, 0, (ops GPRC:$rT, GPRC:$rA),
- "addme $rT, $rA",
+ "addme $rT, $rA", IntGeneral,
[]>;
def ADDZE : XOForm_3<31, 202, 0, (ops GPRC:$rT, GPRC:$rA),
- "addze $rT, $rA",
+ "addze $rT, $rA", IntGeneral,
[]>;
def NEG : XOForm_3<31, 104, 0, (ops GPRC:$rT, GPRC:$rA),
- "neg $rT, $rA",
+ "neg $rT, $rA", IntGeneral,
[(set GPRC:$rT, (ineg GPRC:$rA))]>;
def SUBFZE : XOForm_3<31, 200, 0, (ops GPRC:$rT, GPRC:$rA),
- "subfze $rT, $rA",
+ "subfze $rT, $rA", IntGeneral,
[]>;
// A-Form instructions. Most of the instructions executed in the FPU are of
// this type.
//
def FMADD : AForm_1<63, 29,
- (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
- "fmadd $FRT, $FRA, $FRC, $FRB">;
+ (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
+ "fmadd $FRT, $FRA, $FRC, $FRB", FPFused,
+ [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC),
+ F8RC:$FRB))]>;
def FMADDS : AForm_1<59, 29,
- (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
- "fmadds $FRT, $FRA, $FRC, $FRB">;
+ (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
+ "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
+ [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
+ F4RC:$FRB))]>;
def FMSUB : AForm_1<63, 28,
- (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
- "fmsub $FRT, $FRA, $FRC, $FRB">;
+ (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
+ "fmsub $FRT, $FRA, $FRC, $FRB", FPFused,
+ [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC),
+ F8RC:$FRB))]>;
def FMSUBS : AForm_1<59, 28,
- (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
- "fmsubs $FRT, $FRA, $FRC, $FRB">;
+ (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
+ "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
+ [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC),
+ F4RC:$FRB))]>;
def FNMADD : AForm_1<63, 31,
- (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
- "fnmadd $FRT, $FRA, $FRC, $FRB">;
+ (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
+ "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused,
+ [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC),
+ F8RC:$FRB)))]>;
def FNMADDS : AForm_1<59, 31,
- (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
- "fnmadds $FRT, $FRA, $FRC, $FRB">;
+ (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
+ "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
+ [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC),
+ F4RC:$FRB)))]>;
def FNMSUB : AForm_1<63, 30,
- (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
- "fnmsub $FRT, $FRA, $FRC, $FRB">;
+ (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
+ "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused,
+ [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC),
+ F8RC:$FRB)))]>;
def FNMSUBS : AForm_1<59, 30,
- (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
- "fnmsubs $FRT, $FRA, $FRC, $FRB">;
-def FSEL : AForm_1<63, 23,
- (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
- "fsel $FRT, $FRA, $FRC, $FRB">;
+ (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
+ "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
+ [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC),
+ F4RC:$FRB)))]>;
+// FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
+// having 4 of these, force the comparison to always be an 8-byte double (code
+// should use an FMRSD if the input comparison value really wants to be a float)
+// and 4/8 byte forms for the result and operand type..
+def FSELD : AForm_1<63, 23,
+ (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
+ "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
+ []>;
+def FSELS : AForm_1<63, 23,
+ (ops F4RC:$FRT, F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
+ "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
+ []>;
def FADD : AForm_2<63, 21,
- (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
- "fadd $FRT, $FRA, $FRB">;
+ (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
+ "fadd $FRT, $FRA, $FRB", FPGeneral,
+ [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>;
def FADDS : AForm_2<59, 21,
- (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
- "fadds $FRT, $FRA, $FRB">;
+ (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
+ "fadds $FRT, $FRA, $FRB", FPGeneral,
+ [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>;
def FDIV : AForm_2<63, 18,
- (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
- "fdiv $FRT, $FRA, $FRB">;
+ (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
+ "fdiv $FRT, $FRA, $FRB", FPDivD,
+ [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>;
def FDIVS : AForm_2<59, 18,
- (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
- "fdivs $FRT, $FRA, $FRB">;
+ (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
+ "fdivs $FRT, $FRA, $FRB", FPDivS,
+ [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>;
def FMUL : AForm_3<63, 25,
- (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
- "fmul $FRT, $FRA, $FRB">;
+ (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
+ "fmul $FRT, $FRA, $FRB", FPFused,
+ [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>;
def FMULS : AForm_3<59, 25,
- (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
- "fmuls $FRT, $FRA, $FRB">;
+ (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
+ "fmuls $FRT, $FRA, $FRB", FPGeneral,
+ [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>;
def FSUB : AForm_2<63, 20,
- (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
- "fsub $FRT, $FRA, $FRB">;
+ (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
+ "fsub $FRT, $FRA, $FRB", FPGeneral,
+ [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>;
def FSUBS : AForm_2<59, 20,
- (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
- "fsubs $FRT, $FRA, $FRB">;
+ (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
+ "fsubs $FRT, $FRA, $FRB", FPGeneral,
+ [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>;
// M-Form instructions. rotate and mask instructions.
//
// RLWIMI can be commuted if the rotate amount is zero.
def RLWIMI : MForm_2<20,
(ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
- u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME">;
+ u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate,
+ []>;
+def RLDIMI : MDForm_1<30, 3,
+ (ops G8RC:$rA, G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB),
+ "rldimi $rA, $rS, $SH, $MB", IntRotateD,
+ []>, isPPC64;
}
def RLWINM : MForm_2<21,
(ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
- "rlwinm $rA, $rS, $SH, $MB, $ME">;
+ "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
+ []>;
def RLWINMo : MForm_2<21,
(ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
- "rlwinm. $rA, $rS, $SH, $MB, $ME">, isDOT;
+ "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
+ []>, isDOT;
def RLWNM : MForm_2<23,
(ops GPRC:$rA, GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
- "rlwnm $rA, $rS, $rB, $MB, $ME">;
+ "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral,
+ []>;
// MD-Form instructions. 64 bit rotate instructions.
//
def RLDICL : MDForm_1<30, 0,
- (ops GPRC:$rA, GPRC:$rS, u6imm:$SH, u6imm:$MB),
- "rldicl $rA, $rS, $SH, $MB">, isPPC64;
+ (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$MB),
+ "rldicl $rA, $rS, $SH, $MB", IntRotateD,
+ []>, isPPC64;
def RLDICR : MDForm_1<30, 1,
- (ops GPRC:$rA, GPRC:$rS, u6imm:$SH, u6imm:$ME),
- "rldicr $rA, $rS, $SH, $ME">, isPPC64;
+ (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$ME),
+ "rldicr $rA, $rS, $SH, $ME", IntRotateD,
+ []>, isPPC64;
//===----------------------------------------------------------------------===//
// PowerPC Instruction Patterns
//
-// REDUNDANT WITH INSTRUCTION DEFINITION, ONLY FOR TESTING.
-def : Pat<(sext_inreg GPRC:$in, i8),
- (EXTSB GPRC:$in)>;
-
-// or by an arbitrary immediate.
+// Arbitrary immediate support. Implement in terms of LIS/ORI.
+def : Pat<(i32 imm:$imm),
+ (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
+
+// Implement the 'not' operation with the NOR instruction.
+def NOT : Pat<(not GPRC:$in),
+ (NOR GPRC:$in, GPRC:$in)>;
+
+// ADD an arbitrary immediate.
+def : Pat<(add GPRC:$in, imm:$imm),
+ (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
+// OR an arbitrary immediate.
def : Pat<(or GPRC:$in, imm:$imm),
(ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
-// xor by an arbitrary immediate.
+// XOR an arbitrary immediate.
def : Pat<(xor GPRC:$in, imm:$imm),
(XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
-// Same as above, but using a temporary.
+def : Pat<(zext GPRC:$in),
+ (RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>;
+def : Pat<(anyext GPRC:$in),
+ (OR4To8 GPRC:$in, GPRC:$in)>;
+def : Pat<(trunc G8RC:$in),
+ (OR8To4 G8RC:$in, G8RC:$in)>;
+
+// SHL
+def : Pat<(shl GPRC:$in, imm:$imm),
+ (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>;
+def : Pat<(shl G8RC:$in, imm:$imm),
+ (RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>;
+// SRL
+def : Pat<(srl GPRC:$in, imm:$imm),
+ (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>;
+def : Pat<(srl G8RC:$in, imm:$imm),
+ (RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>;
+
+// Same as above, but using a temporary. FIXME: implement temporaries :)
+/*
def : Pattern<(xor GPRC:$in, imm:$imm),
[(set GPRC:$tmp, (XORI GPRC:$in, (LO16 imm:$imm))),
(XORIS GPRC:$tmp, (HI16 imm:$imm))]>;
+*/
//===----------------------------------------------------------------------===//
projects / oota-llvm.git / blobdiff