Rework PPC64 calls. Now we have a LR8/CTR8 register which the PPC64 calls

[oota-llvm.git] / lib / Target / PowerPC / PPCInstrInfo.td

diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td
index 2ab5d552e8459df98b7fe212c23aa84a54f0c090..4ffd98c682e419149e3c692a18c2f51b4193ae86 100644 (file)
--- a/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/lib/Target/PowerPC/PPCInstrInfo.td
@@ -197,6 +197,9 @@ class isDOT   {
   bit RC  = 1;
 }
 
+class RegConstraint<string C> {
+  string Constraints = C;
+}
 
 
 //===----------------------------------------------------------------------===//
@@ -244,20 +247,23 @@ def crbitm: Operand<i8> {
 // Address operands
 def memri : Operand<iPTR> {
   let PrintMethod = "printMemRegImm";
-  let NumMIOperands = 2;
   let MIOperandInfo = (ops i32imm, ptr_rc);
 }
 def memrr : Operand<iPTR> {
   let PrintMethod = "printMemRegReg";
-  let NumMIOperands = 2;
   let MIOperandInfo = (ops ptr_rc, ptr_rc);
 }
 def memrix : Operand<iPTR> {   // memri where the imm is shifted 2 bits.
   let PrintMethod = "printMemRegImmShifted";
-  let NumMIOperands = 2;
   let MIOperandInfo = (ops i32imm, ptr_rc);
 }
 
+// PowerPC Predicate operand.  20 = (0<<5)|20 = always, CR0 is a dummy reg
+// that doesn't matter.
+def pred : PredicateOperand<(ops imm, CRRC), (ops (i32 20), CR0)> {
+  let PrintMethod = "printPredicateOperand";
+}
+
 // Define PowerPC specific addressing mode.
 def iaddr  : ComplexPattern<iPTR, 2, "SelectAddrImm",    [], []>;
 def xaddr  : ComplexPattern<iPTR, 2, "SelectAddrIdx",    [], []>;
@@ -268,6 +274,7 @@ def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std"
 // PowerPC Instruction Predicate Definitions.
 def FPContractions : Predicate<"!NoExcessFPPrecision">;
 
+
 //===----------------------------------------------------------------------===//
 // PowerPC Instruction Definitions.
 
@@ -314,10 +321,15 @@ let usesCustomDAGSchedInserter = 1,    // Expanded by the scheduler.
 
 let isTerminator = 1, isBarrier = 1, noResults = 1, PPC970_Unit = 7 in {
   let isReturn = 1 in
-    def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr", BrB, [(retflag)]>;
+    def BLR : XLForm_2_br<19, 16, 0,
+                          (ops pred:$p),
+                          "b${p:cc}lr ${p:reg}", BrB, 
+                          [(retflag)]>;
   def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr", BrB, []>;
 }
 
+
+
 let Defs = [LR] in
   def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label", []>,
                    PPC970_Unit_BRU;
@@ -411,10 +423,48 @@ def LHZ : DForm_1<40, (ops GPRC:$rD, memri:$src),
 def LWZ : DForm_1<32, (ops GPRC:$rD, memri:$src),
                   "lwz $rD, $src", LdStGeneral,
                   [(set GPRC:$rD, (load iaddr:$src))]>;
-def LWZU : DForm_1<35, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
+
+def LFS : DForm_1<48, (ops F4RC:$rD, memri:$src),
+                  "lfs $rD, $src", LdStLFDU,
+                  [(set F4RC:$rD, (load iaddr:$src))]>;
+def LFD : DForm_1<50, (ops F8RC:$rD, memri:$src),
+                  "lfd $rD, $src", LdStLFD,
+                  [(set F8RC:$rD, (load iaddr:$src))]>;
+
+// FIXME: PTRRC for Pointer regs for ppc64.
+
+// 'Update' load forms.
+def LBZU : DForm_1<35, (ops GPRC:$rD, ptr_rc:$rA_result, symbolLo:$disp,
+                            ptr_rc:$rA),
+                   "lbzu $rD, $disp($rA)", LdStGeneral,
+                   []>, RegConstraint<"$rA = $rA_result">;
+
+def LHAU : DForm_1<43, (ops GPRC:$rD, ptr_rc:$rA_result, symbolLo:$disp,
+                            ptr_rc:$rA),
+                   "lhau $rD, $disp($rA)", LdStGeneral,
+                   []>, RegConstraint<"$rA = $rA_result">;
+
+def LHZU : DForm_1<41, (ops GPRC:$rD, ptr_rc:$rA_result, symbolLo:$disp,
+                            ptr_rc:$rA),
+                   "lhzu $rD, $disp($rA)", LdStGeneral,
+                   []>, RegConstraint<"$rA = $rA_result">;
+
+def LWZU : DForm_1<33, (ops GPRC:$rD, ptr_rc:$rA_result, symbolLo:$disp,
+                            ptr_rc:$rA),
                    "lwzu $rD, $disp($rA)", LdStGeneral,
-                   []>;
+                   []>, RegConstraint<"$rA = $rA_result">;
+
+def LFSU : DForm_1<49, (ops F4RC:$rD, ptr_rc:$rA_result, symbolLo:$disp,
+                            ptr_rc:$rA),
+                  "lfs $rD, $disp($rA)", LdStLFDU,
+                  []>, RegConstraint<"$rA = $rA_result">;
+def LFDU : DForm_1<51, (ops F8RC:$rD, ptr_rc:$rA_result, symbolLo:$disp,
+                            ptr_rc:$rA),
+                  "lfd $rD, $disp($rA)", LdStLFD,
+                  []>, RegConstraint<"$rA = $rA_result">;
 }
+
+
 let PPC970_Unit = 1 in {  // FXU Operations.
 def ADDI   : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
                      "addi $rD, $rA, $imm", IntGeneral,
@@ -488,19 +538,11 @@ def CMPWI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
 def CMPLWI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
                          "cmplwi $dst, $src1, $src2", IntCompare>;
 }
-let isLoad = 1, PPC970_Unit = 2 in {
-def LFS : DForm_8<48, (ops F4RC:$rD, memri:$src),
-                  "lfs $rD, $src", LdStLFDU,
-                  [(set F4RC:$rD, (load iaddr:$src))]>;
-def LFD : DForm_8<50, (ops F8RC:$rD, memri:$src),
-                  "lfd $rD, $src", LdStLFD,
-                  [(set F8RC:$rD, (load iaddr:$src))]>;
-}
 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
-def STFS : DForm_9<52, (ops F4RC:$rS, memri:$dst),
+def STFS : DForm_1<52, (ops F4RC:$rS, memri:$dst),
                    "stfs $rS, $dst", LdStUX,
                    [(store F4RC:$rS, iaddr:$dst)]>;
-def STFD : DForm_9<54, (ops F8RC:$rS, memri:$dst),
+def STFD : DForm_1<54, (ops F8RC:$rS, memri:$dst),
                    "stfd $rS, $dst", LdStUX,
                    [(store F8RC:$rS, iaddr:$dst)]>;
 }
@@ -974,9 +1016,9 @@ def : Pat<(and (rotl GPRC:$in, GPRC:$sh), maskimm32:$imm),
           (RLWNM GPRC:$in, GPRC:$sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
 
 // Calls
-def : Pat<(PPCcall tglobaladdr:$dst),
+def : Pat<(PPCcall (i32 tglobaladdr:$dst)),
           (BL tglobaladdr:$dst)>;
-def : Pat<(PPCcall texternalsym:$dst),
+def : Pat<(PPCcall (i32 texternalsym:$dst)),
           (BL texternalsym:$dst)>;
 
 // Hi and Lo for Darwin Global Addresses.