def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore, [SDNPHasChain]>;
// These are target-independent nodes, but have target-specific formats.
-def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeq,[SDNPHasChain]>;
-def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeq,[SDNPHasChain]>;
+def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeq,
+ [SDNPHasChain, SDNPOutFlag]>;
+def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeq,
+ [SDNPHasChain, SDNPOutFlag]>;
def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall,
signed int Val = N->getValue();
return getI32Imm((Val - (signed short)Val) >> 16);
}]>;
+def MB : SDNodeXForm<imm, [{
+ // Transformation function: get the start bit of a mask
+ unsigned mb, me;
+ (void)isRunOfOnes((unsigned)N->getValue(), mb, me);
+ return getI32Imm(mb);
+}]>;
+def ME : SDNodeXForm<imm, [{
+ // Transformation function: get the end bit of a mask
+ unsigned mb, me;
+ (void)isRunOfOnes((unsigned)N->getValue(), mb, me);
+ return getI32Imm(me);
+}]>;
+def maskimm32 : PatLeaf<(imm), [{
+ // maskImm predicate - True if immediate is a run of ones.
+ unsigned mb, me;
+ if (N->getValueType(0) == MVT::i32)
+ return isRunOfOnes((unsigned)N->getValue(), mb, me);
+ else
+ return false;
+}]>;
def immSExt16 : PatLeaf<(imm), [{
// immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
bit RC = 1;
}
+class RegConstraint<string C> {
+ string Constraints = C;
+}
//===----------------------------------------------------------------------===//
// Address operands
def memri : Operand<iPTR> {
let PrintMethod = "printMemRegImm";
- let NumMIOperands = 2;
let MIOperandInfo = (ops i32imm, ptr_rc);
}
def memrr : Operand<iPTR> {
let PrintMethod = "printMemRegReg";
- let NumMIOperands = 2;
let MIOperandInfo = (ops ptr_rc, ptr_rc);
}
def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits.
let PrintMethod = "printMemRegImmShifted";
- let NumMIOperands = 2;
let MIOperandInfo = (ops i32imm, ptr_rc);
}
+// PowerPC Predicate operand. 20 = (0<<5)|20 = always, CR0 is a dummy reg
+// that doesn't matter.
+def pred : PredicateOperand<(ops imm, CRRC), (ops (i32 20), CR0)> {
+ let PrintMethod = "printPredicateOperand";
+}
+
// Define PowerPC specific addressing mode.
-def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", []>;
-def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", []>;
-def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[]>;
-def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", []>; // "std"
+def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
+def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
+def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
+def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std"
//===----------------------------------------------------------------------===//
// PowerPC Instruction Predicate Definitions.
def FPContractions : Predicate<"!NoExcessFPPrecision">;
+
//===----------------------------------------------------------------------===//
// PowerPC Instruction Definitions.
let hasCtrlDep = 1 in {
def ADJCALLSTACKDOWN : Pseudo<(ops u16imm:$amt),
- "; ADJCALLSTACKDOWN",
- [(callseq_start imm:$amt)]>;
+ "${:comment} ADJCALLSTACKDOWN",
+ [(callseq_start imm:$amt)]>, Imp<[R1],[R1]>;
def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt),
- "; ADJCALLSTACKUP",
- [(callseq_end imm:$amt)]>;
+ "${:comment} ADJCALLSTACKUP",
+ [(callseq_end imm:$amt)]>, Imp<[R1],[R1]>;
def UPDATE_VRSAVE : Pseudo<(ops GPRC:$rD, GPRC:$rS),
"UPDATE_VRSAVE $rD, $rS", []>;
}
-def IMPLICIT_DEF_GPRC: Pseudo<(ops GPRC:$rD), "; IMPLICIT_DEF_GPRC $rD",
+def IMPLICIT_DEF_GPRC: Pseudo<(ops GPRC:$rD),"${:comment}IMPLICIT_DEF_GPRC $rD",
[(set GPRC:$rD, (undef))]>;
-def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "; IMPLICIT_DEF_F8 $rD",
+def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "${:comment} IMPLICIT_DEF_F8 $rD",
[(set F8RC:$rD, (undef))]>;
-def IMPLICIT_DEF_F4 : Pseudo<(ops F4RC:$rD), "; IMPLICIT_DEF_F4 $rD",
+def IMPLICIT_DEF_F4 : Pseudo<(ops F4RC:$rD), "${:comment} IMPLICIT_DEF_F4 $rD",
[(set F4RC:$rD, (undef))]>;
// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
let usesCustomDAGSchedInserter = 1, // Expanded by the scheduler.
PPC970_Single = 1 in {
def SELECT_CC_I4 : Pseudo<(ops GPRC:$dst, CRRC:$cond, GPRC:$T, GPRC:$F,
- i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
+ i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
+ []>;
def SELECT_CC_I8 : Pseudo<(ops G8RC:$dst, CRRC:$cond, G8RC:$T, G8RC:$F,
- i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
+ i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
+ []>;
def SELECT_CC_F4 : Pseudo<(ops F4RC:$dst, CRRC:$cond, F4RC:$T, F4RC:$F,
- i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
+ i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
+ []>;
def SELECT_CC_F8 : Pseudo<(ops F8RC:$dst, CRRC:$cond, F8RC:$T, F8RC:$F,
- i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
+ i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
+ []>;
def SELECT_CC_VRRC: Pseudo<(ops VRRC:$dst, CRRC:$cond, VRRC:$T, VRRC:$F,
- i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
+ i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
+ []>;
}
-let isTerminator = 1, noResults = 1, PPC970_Unit = 7 in {
+let isTerminator = 1, isBarrier = 1, noResults = 1, PPC970_Unit = 7 in {
let isReturn = 1 in
- def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr", BrB, [(retflag)]>;
+ def BLR : XLForm_2_br<19, 16, 0,
+ (ops pred:$p),
+ "b${p:cc}lr ${p:reg}", BrB,
+ [(retflag)]>;
def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr", BrB, []>;
}
+
+
let Defs = [LR] in
def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label", []>,
PPC970_Unit_BRU;
let isBranch = 1, isTerminator = 1, hasCtrlDep = 1,
noResults = 1, PPC970_Unit = 7 in {
+ // COND_BRANCH is formed before branch selection, it is turned into Bcc below.
def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm:$opc, target:$dst),
- "; COND_BRANCH $crS, $opc, $dst",
+ "${:comment} COND_BRANCH $crS, $opc, $dst",
[(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]>;
+ let isBarrier = 1 in {
def B : IForm<18, 0, 0, (ops target:$dst),
"b $dst", BrB,
[(br bb:$dst)]>;
+ }
def BLT : BForm<16, 0, 0, 12, 0, (ops CRRC:$crS, target:$block),
"blt $crS, $block", BrB>;
}
// DCB* instructions.
-def DCBZ : DCB_Form<1014, 0, (ops memrr:$dst),
- "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
- PPC970_DGroup_Single;
-def DCBZL : DCB_Form<1014, 1, (ops memrr:$dst),
- "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
- PPC970_DGroup_Single;
+def DCBA : DCB_Form<758, 0, (ops memrr:$dst),
+ "dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
+ PPC970_DGroup_Single;
+def DCBF : DCB_Form<86, 0, (ops memrr:$dst),
+ "dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
+ PPC970_DGroup_Single;
+def DCBI : DCB_Form<470, 0, (ops memrr:$dst),
+ "dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
+ PPC970_DGroup_Single;
+def DCBST : DCB_Form<54, 0, (ops memrr:$dst),
+ "dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
+ PPC970_DGroup_Single;
+def DCBT : DCB_Form<278, 0, (ops memrr:$dst),
+ "dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
+ PPC970_DGroup_Single;
+def DCBTST : DCB_Form<246, 0, (ops memrr:$dst),
+ "dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
+ PPC970_DGroup_Single;
+def DCBZ : DCB_Form<1014, 0, (ops memrr:$dst),
+ "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
+ PPC970_DGroup_Single;
+def DCBZL : DCB_Form<1014, 1, (ops memrr:$dst),
+ "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
+ PPC970_DGroup_Single;
// D-Form instructions. Most instructions that perform an operation on a
// register and an immediate are of this type.
let isLoad = 1, PPC970_Unit = 2 in {
def LBZ : DForm_1<34, (ops GPRC:$rD, memri:$src),
"lbz $rD, $src", LdStGeneral,
- [(set GPRC:$rD, (zextload iaddr:$src, i8))]>;
+ [(set GPRC:$rD, (zextloadi8 iaddr:$src))]>;
def LHA : DForm_1<42, (ops GPRC:$rD, memri:$src),
"lha $rD, $src", LdStLHA,
- [(set GPRC:$rD, (sextload iaddr:$src, i16))]>,
+ [(set GPRC:$rD, (sextloadi16 iaddr:$src))]>,
PPC970_DGroup_Cracked;
def LHZ : DForm_1<40, (ops GPRC:$rD, memri:$src),
"lhz $rD, $src", LdStGeneral,
- [(set GPRC:$rD, (zextload iaddr:$src, i16))]>;
+ [(set GPRC:$rD, (zextloadi16 iaddr:$src))]>;
def LWZ : DForm_1<32, (ops GPRC:$rD, memri:$src),
"lwz $rD, $src", LdStGeneral,
[(set GPRC:$rD, (load iaddr:$src))]>;
-def LWZU : DForm_1<35, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
+
+def LFS : DForm_1<48, (ops F4RC:$rD, memri:$src),
+ "lfs $rD, $src", LdStLFDU,
+ [(set F4RC:$rD, (load iaddr:$src))]>;
+def LFD : DForm_1<50, (ops F8RC:$rD, memri:$src),
+ "lfd $rD, $src", LdStLFD,
+ [(set F8RC:$rD, (load iaddr:$src))]>;
+
+// FIXME: PTRRC for Pointer regs for ppc64.
+
+// 'Update' load forms.
+def LBZU : DForm_1<35, (ops GPRC:$rD, ptr_rc:$rA_result, symbolLo:$disp,
+ ptr_rc:$rA),
+ "lbzu $rD, $disp($rA)", LdStGeneral,
+ []>, RegConstraint<"$rA = $rA_result">;
+
+def LHAU : DForm_1<43, (ops GPRC:$rD, ptr_rc:$rA_result, symbolLo:$disp,
+ ptr_rc:$rA),
+ "lhau $rD, $disp($rA)", LdStGeneral,
+ []>, RegConstraint<"$rA = $rA_result">;
+
+def LHZU : DForm_1<41, (ops GPRC:$rD, ptr_rc:$rA_result, symbolLo:$disp,
+ ptr_rc:$rA),
+ "lhzu $rD, $disp($rA)", LdStGeneral,
+ []>, RegConstraint<"$rA = $rA_result">;
+
+def LWZU : DForm_1<33, (ops GPRC:$rD, ptr_rc:$rA_result, symbolLo:$disp,
+ ptr_rc:$rA),
"lwzu $rD, $disp($rA)", LdStGeneral,
- []>;
+ []>, RegConstraint<"$rA = $rA_result">;
+
+def LFSU : DForm_1<49, (ops F4RC:$rD, ptr_rc:$rA_result, symbolLo:$disp,
+ ptr_rc:$rA),
+ "lfs $rD, $disp($rA)", LdStLFDU,
+ []>, RegConstraint<"$rA = $rA_result">;
+def LFDU : DForm_1<51, (ops F8RC:$rD, ptr_rc:$rA_result, symbolLo:$disp,
+ ptr_rc:$rA),
+ "lfd $rD, $disp($rA)", LdStLFD,
+ []>, RegConstraint<"$rA = $rA_result">;
}
+
+
let PPC970_Unit = 1 in { // FXU Operations.
def ADDI : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
"addi $rD, $rA, $imm", IntGeneral,
let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
def STB : DForm_3<38, (ops GPRC:$rS, memri:$src),
"stb $rS, $src", LdStGeneral,
- [(truncstore GPRC:$rS, iaddr:$src, i8)]>;
+ [(truncstorei8 GPRC:$rS, iaddr:$src)]>;
def STH : DForm_3<44, (ops GPRC:$rS, memri:$src),
"sth $rS, $src", LdStGeneral,
- [(truncstore GPRC:$rS, iaddr:$src, i16)]>;
+ [(truncstorei16 GPRC:$rS, iaddr:$src)]>;
def STW : DForm_3<36, (ops GPRC:$rS, memri:$src),
"stw $rS, $src", LdStGeneral,
[(store GPRC:$rS, iaddr:$src)]>;
def CMPLWI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
"cmplwi $dst, $src1, $src2", IntCompare>;
}
-let isLoad = 1, PPC970_Unit = 2 in {
-def LFS : DForm_8<48, (ops F4RC:$rD, memri:$src),
- "lfs $rD, $src", LdStLFDU,
- [(set F4RC:$rD, (load iaddr:$src))]>;
-def LFD : DForm_8<50, (ops F8RC:$rD, memri:$src),
- "lfd $rD, $src", LdStLFD,
- [(set F8RC:$rD, (load iaddr:$src))]>;
-}
let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
-def STFS : DForm_9<52, (ops F4RC:$rS, memri:$dst),
+def STFS : DForm_1<52, (ops F4RC:$rS, memri:$dst),
"stfs $rS, $dst", LdStUX,
[(store F4RC:$rS, iaddr:$dst)]>;
-def STFD : DForm_9<54, (ops F8RC:$rS, memri:$dst),
+def STFD : DForm_1<54, (ops F8RC:$rS, memri:$dst),
"stfd $rS, $dst", LdStUX,
[(store F8RC:$rS, iaddr:$dst)]>;
}
let isLoad = 1, PPC970_Unit = 2 in {
def LBZX : XForm_1<31, 87, (ops GPRC:$rD, memrr:$src),
"lbzx $rD, $src", LdStGeneral,
- [(set GPRC:$rD, (zextload xaddr:$src, i8))]>;
+ [(set GPRC:$rD, (zextloadi8 xaddr:$src))]>;
def LHAX : XForm_1<31, 343, (ops GPRC:$rD, memrr:$src),
"lhax $rD, $src", LdStLHA,
- [(set GPRC:$rD, (sextload xaddr:$src, i16))]>,
+ [(set GPRC:$rD, (sextloadi16 xaddr:$src))]>,
PPC970_DGroup_Cracked;
def LHZX : XForm_1<31, 279, (ops GPRC:$rD, memrr:$src),
"lhzx $rD, $src", LdStGeneral,
- [(set GPRC:$rD, (zextload xaddr:$src, i16))]>;
+ [(set GPRC:$rD, (zextloadi16 xaddr:$src))]>;
def LWZX : XForm_1<31, 23, (ops GPRC:$rD, memrr:$src),
"lwzx $rD, $src", LdStGeneral,
[(set GPRC:$rD, (load xaddr:$src))]>;
let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
def STBX : XForm_8<31, 215, (ops GPRC:$rS, memrr:$dst),
"stbx $rS, $dst", LdStGeneral,
- [(truncstore GPRC:$rS, xaddr:$dst, i8)]>,
+ [(truncstorei8 GPRC:$rS, xaddr:$dst)]>,
PPC970_DGroup_Cracked;
def STHX : XForm_8<31, 407, (ops GPRC:$rS, memrr:$dst),
"sthx $rS, $dst", LdStGeneral,
- [(truncstore GPRC:$rS, xaddr:$dst, i16)]>,
+ [(truncstorei16 GPRC:$rS, xaddr:$dst)]>,
PPC970_DGroup_Cracked;
def STWX : XForm_8<31, 151, (ops GPRC:$rS, memrr:$dst),
"stwx $rS, $dst", LdStGeneral,
//
def DWARF_LOC : Pseudo<(ops i32imm:$line, i32imm:$col, i32imm:$file),
- "; .loc $file, $line, $col",
+ "${:comment} .loc $file, $line, $col",
[(dwarf_loc (i32 imm:$line), (i32 imm:$col),
(i32 imm:$file))]>;
def DWARF_LABEL : Pseudo<(ops i32imm:$id),
- "\nLdebug_loc$id:",
+ "\n${:private}debug_loc$id:",
[(dwarf_label (i32 imm:$id))]>;
//===----------------------------------------------------------------------===//
def : Pat<(rotl GPRC:$in, (i32 imm:$imm)),
(RLWINM GPRC:$in, imm:$imm, 0, 31)>;
+// RLWNM
+def : Pat<(and (rotl GPRC:$in, GPRC:$sh), maskimm32:$imm),
+ (RLWNM GPRC:$in, GPRC:$sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
+
// Calls
-def : Pat<(PPCcall tglobaladdr:$dst),
+def : Pat<(PPCcall (i32 tglobaladdr:$dst)),
(BL tglobaladdr:$dst)>;
-def : Pat<(PPCcall texternalsym:$dst),
+def : Pat<(PPCcall (i32 texternalsym:$dst)),
(BL texternalsym:$dst)>;
// Hi and Lo for Darwin Global Addresses.
def : Pat<(shl GPRC:$rS, GPRC:$rB),
(SLW GPRC:$rS, GPRC:$rB)>;
-def : Pat<(zextload iaddr:$src, i1),
+def : Pat<(zextloadi1 iaddr:$src),
(LBZ iaddr:$src)>;
-def : Pat<(zextload xaddr:$src, i1),
+def : Pat<(zextloadi1 xaddr:$src),
(LBZX xaddr:$src)>;
-def : Pat<(extload iaddr:$src, i1),
+def : Pat<(extloadi1 iaddr:$src),
(LBZ iaddr:$src)>;
-def : Pat<(extload xaddr:$src, i1),
+def : Pat<(extloadi1 xaddr:$src),
(LBZX xaddr:$src)>;
-def : Pat<(extload iaddr:$src, i8),
+def : Pat<(extloadi8 iaddr:$src),
(LBZ iaddr:$src)>;
-def : Pat<(extload xaddr:$src, i8),
+def : Pat<(extloadi8 xaddr:$src),
(LBZX xaddr:$src)>;
-def : Pat<(extload iaddr:$src, i16),
+def : Pat<(extloadi16 iaddr:$src),
(LHZ iaddr:$src)>;
-def : Pat<(extload xaddr:$src, i16),
+def : Pat<(extloadi16 xaddr:$src),
(LHZX xaddr:$src)>;
-def : Pat<(extload iaddr:$src, f32),
+def : Pat<(extloadf32 iaddr:$src),
(FMRSD (LFS iaddr:$src))>;
-def : Pat<(extload xaddr:$src, f32),
+def : Pat<(extloadf32 xaddr:$src),
(FMRSD (LFSX xaddr:$src))>;
include "PPCInstrAltivec.td"
projects / oota-llvm.git / blobdiff