dform 8/9 are identical to dform 1

[oota-llvm.git] / lib / Target / PowerPC / PPCInstrFormats.td

diff --git a/lib/Target/PowerPC/PPCInstrFormats.td b/lib/Target/PowerPC/PPCInstrFormats.td
index 9f87b278e674d18039344b69f766db667c501b2b..2237beb9d24161279285f5f49cdf4d416a254604 100644 (file)
--- a/lib/Target/PowerPC/PPCInstrFormats.td
+++ b/lib/Target/PowerPC/PPCInstrFormats.td
@@ -16,7 +16,6 @@ class I<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin>
   field bits<32> Inst;
 
   bit PPC64 = 0;  // Default value, override with isPPC64
-  bit VMX = 0;    // Default value, override with isVMX
 
   let Name = "";
   let Namespace = "PPC";
@@ -175,15 +174,6 @@ class DForm_6_ext<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin>
   let L = PPC64;
 }
 
-class DForm_8<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin,
-              list<dag> pattern>
-  : DForm_1<opcode, OL, asmstr, itin, pattern> {
-}
-
-class DForm_9<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin,
-              list<dag> pattern>
-  : DForm_1<opcode, OL, asmstr, itin, pattern> {
-}
 
 // 1.7.5 DS-Form
 class DSForm_1<bits<6> opcode, bits<2> xo, dag OL, string asmstr,
@@ -325,6 +315,43 @@ class XForm_28<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
   : XForm_base_r3xo<opcode, xo, OL, asmstr, itin, pattern> {
 }
 
+// DCB_Form - Form X instruction, used for dcb* instructions.
+class DCB_Form<bits<10> xo, bits<5> immfield, dag OL, string asmstr, 
+                      InstrItinClass itin, list<dag> pattern>
+  : I<31, OL, asmstr, itin> {
+  bits<5> A;
+  bits<5> B;
+
+  let Pattern = pattern;
+
+  let Inst{6-10}  = immfield;
+  let Inst{11-15} = A;
+  let Inst{16-20} = B;
+  let Inst{21-30} = xo;
+  let Inst{31}    = 0;
+}
+
+
+// DSS_Form - Form X instruction, used for altivec dss* instructions.
+class DSS_Form<bits<10> xo, dag OL, string asmstr, 
+                      InstrItinClass itin, list<dag> pattern>
+  : I<31, OL, asmstr, itin> {
+  bits<1> T;
+  bits<2> STRM;
+  bits<5> A;
+  bits<5> B;
+
+  let Pattern = pattern;
+
+  let Inst{6}     = T;
+  let Inst{7-8}   = 0;
+  let Inst{9-10}  = STRM;
+  let Inst{11-15} = A;
+  let Inst{16-20} = B;
+  let Inst{21-30} = xo;
+  let Inst{31}    = 0;
+}
+
 // 1.7.7 XL-Form
 class XLForm_1<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
                InstrItinClass itin>
@@ -363,6 +390,19 @@ class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OL, string asmstr,
   let Inst{31}    = lk;
 }
 
+class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk,
+                  dag OL, string asmstr, InstrItinClass itin, list<dag> pattern>
+  : XLForm_2<opcode, xo, lk, OL, asmstr, itin, pattern> {
+  bits<7> BIBO;  // 2 bits of BI and 5 bits of BO.
+  bits<3>  CR;
+  
+  let BO = BIBO{2-6};
+  let BI{0-1} = BIBO{0-1};
+  let BI{2-4} = CR;
+  let BH = 0;
+}
+
+
 class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo,  bits<5> bi, bit lk,
                   dag OL, string asmstr, InstrItinClass itin, list<dag> pattern>
   : XLForm_2<opcode, xo, lk, OL, asmstr, itin, pattern> {
@@ -465,13 +505,14 @@ class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
 
 // 1.7.10 XS-Form
 class XSForm_1<bits<6> opcode, bits<9> xo, dag OL, string asmstr,
-               InstrItinClass itin>
+               InstrItinClass itin, list<dag> pattern>
          : I<opcode, OL, asmstr, itin> {
   bits<5> RS;
   bits<5> A;
   bits<6> SH;
 
   bit RC = 0;    // set by isDOT
+  let Pattern = pattern;
 
   let Inst{6-10}  = RS;
   let Inst{11-15} = A;
@@ -571,8 +612,8 @@ class MForm_2<bits<6> opcode, dag OL, string asmstr,
 class MDForm_1<bits<6> opcode, bits<3> xo, dag OL, string asmstr,
                InstrItinClass itin, list<dag> pattern>
     : I<opcode, OL, asmstr, itin> {
-  bits<5> RS;
   bits<5> RA;
+  bits<5> RS;
   bits<6> SH;
   bits<6> MBE;
 
@@ -582,14 +623,18 @@ class MDForm_1<bits<6> opcode, bits<3> xo, dag OL, string asmstr,
 
   let Inst{6-10}  = RS;
   let Inst{11-15} = RA;
-  let Inst{16-20} = SH{1-5};
-  let Inst{21-26} = MBE;
+  let Inst{16-20} = { SH{4}, SH{3}, SH{2}, SH{1}, SH{0} };
+  let Inst{21-26} = { MBE{4}, MBE{3}, MBE{2}, MBE{1}, MBE{0}, MBE{5} };
   let Inst{27-29} = xo;
-  let Inst{30}    = SH{0};
+  let Inst{30}    = SH{5};
   let Inst{31}    = RC;
 }
 
+
+
 // E-1 VA-Form
+
+// VAForm_1 - DACB ordering.
 class VAForm_1<bits<6> xo, dag OL, string asmstr,
                InstrItinClass itin, list<dag> pattern>
     : I<4, OL, asmstr, itin> {
@@ -607,6 +652,24 @@ class VAForm_1<bits<6> xo, dag OL, string asmstr,
   let Inst{26-31} = xo;
 }
 
+// VAForm_1a - DABC ordering.
+class VAForm_1a<bits<6> xo, dag OL, string asmstr,
+                InstrItinClass itin, list<dag> pattern>
+    : I<4, OL, asmstr, itin> {
+  bits<5> VD;
+  bits<5> VA;
+  bits<5> VB;
+  bits<5> VC;
+
+  let Pattern = pattern;
+  
+  let Inst{6-10}  = VD;
+  let Inst{11-15} = VA;
+  let Inst{16-20} = VB;
+  let Inst{21-25} = VC;
+  let Inst{26-31} = xo;
+}
+
 class VAForm_2<bits<6> xo, dag OL, string asmstr,
                InstrItinClass itin, list<dag> pattern>
     : I<4, OL, asmstr, itin> {
@@ -677,6 +740,33 @@ class VXForm_3<bits<11> xo, dag OL, string asmstr,
   let Inst{21-31} = xo;
 }
 
+/// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr.
+class VXForm_4<bits<11> xo, dag OL, string asmstr,
+               InstrItinClass itin, list<dag> pattern>
+    : I<4, OL, asmstr, itin> {
+  bits<5> VD;
+  
+  let Pattern = pattern;
+  
+  let Inst{6-10}  = VD;
+  let Inst{11-15} = 0;
+  let Inst{16-20} = 0;
+  let Inst{21-31} = xo;
+}
+
+/// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr.
+class VXForm_5<bits<11> xo, dag OL, string asmstr,
+               InstrItinClass itin, list<dag> pattern>
+    : I<4, OL, asmstr, itin> {
+  bits<5> VB;
+  
+  let Pattern = pattern;
+  
+  let Inst{6-10}  = 0;
+  let Inst{11-15} = 0;
+  let Inst{16-20} = VB;
+  let Inst{21-31} = xo;
+}
 
 // E-4 VXR-Form
 class VXRForm_1<bits<10> xo, dag OL, string asmstr,
@@ -700,7 +790,6 @@ class VXRForm_1<bits<10> xo, dag OL, string asmstr,
 class Pseudo<dag OL, string asmstr, list<dag> pattern>
     : I<0, OL, asmstr, NoItinerary> {
   let PPC64 = 0;
-  let VMX = 0;
   let Pattern = pattern;
   let Inst{31-0} = 0;
 }