Add all of the data stream intrinsics and instructions. woo

[oota-llvm.git] / lib / Target / PowerPC / PPCInstrAltivec.td

diff --git a/lib/Target/PowerPC/PPCInstrAltivec.td b/lib/Target/PowerPC/PPCInstrAltivec.td
index 0ff29391212e88a1059f447b5910f32845315394..6cac3ec40d865645cd945530999c9f77644daa0d 100644 (file)
--- a/lib/Target/PowerPC/PPCInstrAltivec.td
+++ b/lib/Target/PowerPC/PPCInstrAltivec.td
@@ -93,6 +93,15 @@ class VX2_Int<bits<11> xo, string opc, Intrinsic IntID>
 def IMPLICIT_DEF_VRRC : Pseudo<(ops VRRC:$rD), "; $rD = IMPLICIT_DEF_VRRC",
                                [(set VRRC:$rD, (v4f32 (undef)))]>;
 
+let noResults = 1 in {
+def DSS   : DSS_Form<822, (ops u5imm:$A, u5imm:$STRM,u5imm:$ZERO1,u5imm:$ZERO2),
+                     "dss $STRM, $A", LdStGeneral /*FIXME*/, []>;
+def DST   : DSS_Form<342, (ops u5imm:$T, u5imm:$STRM, GPRC:$rA, GPRC:$rB),
+                     "dst $rA, $rB, $STRM, $T", LdStGeneral /*FIXME*/, []>;
+def DSTST : DSS_Form<374, (ops u5imm:$T, u5imm:$STRM, GPRC:$rA, GPRC:$rB),
+                   "dstst $rA, $rB, $STRM, $T", LdStGeneral /*FIXME*/, []>;
+}
+
 def MFVSCR : VXForm_4<1540, (ops VRRC:$vD),
                       "mfvcr $vD", LdStGeneral,
                       [(set VRRC:$vD, (int_ppc_altivec_mfvscr))]>; 
@@ -123,7 +132,7 @@ def LVSL : XForm_1<31,   6, (ops VRRC:$vD, memrr:$src),
                    [(set VRRC:$vD, (int_ppc_altivec_lvsl xoaddr:$src))]>,
                    PPC970_Unit_LSU;
 def LVSR : XForm_1<31,  38, (ops VRRC:$vD, memrr:$src),
-                   "lvsl $vD, $src", LdStGeneral,
+                   "lvsr $vD, $src", LdStGeneral,
                    [(set VRRC:$vD, (int_ppc_altivec_lvsr xoaddr:$src))]>,
                    PPC970_Unit_LSU;
 
@@ -312,6 +321,8 @@ def VXOR : VXForm_1<1220, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
 def VRLB   : VX1_Int<   4, "vrlb", int_ppc_altivec_vrlb>;
 def VRLH   : VX1_Int<  68, "vrlh", int_ppc_altivec_vrlh>;
 def VRLW   : VX1_Int< 132, "vrlw", int_ppc_altivec_vrlw>;
+
+def VSL    : VX1_Int< 452, "vsl" , int_ppc_altivec_vsl >;
 def VSLO   : VX1_Int<1036, "vslo", int_ppc_altivec_vslo>;
 def VSLB   : VX1_Int< 260, "vslb", int_ppc_altivec_vslb>;
 def VSLH   : VX1_Int< 324, "vslh", int_ppc_altivec_vslh>;
@@ -429,6 +440,18 @@ def V_SET0 : VXForm_setzero<1220, (ops VRRC:$vD),
 // Additional Altivec Patterns
 //
 
+// DS* intrinsics.
+def : Pat<(int_ppc_altivec_dss imm:$STRM), (DSS 0, imm:$STRM, 0, 0)>;
+def : Pat<(int_ppc_altivec_dssall), (DSS 1, 0, 0, 0)>;
+def : Pat<(int_ppc_altivec_dst GPRC:$rA, GPRC:$rB, imm:$STRM),
+          (DST 0, imm:$STRM, GPRC:$rA, GPRC:$rB)>;
+def : Pat<(int_ppc_altivec_dstt GPRC:$rA, GPRC:$rB, imm:$STRM),
+          (DST 1, imm:$STRM, GPRC:$rA, GPRC:$rB)>;
+def : Pat<(int_ppc_altivec_dstst GPRC:$rA, GPRC:$rB, imm:$STRM),
+          (DSTST 0, imm:$STRM, GPRC:$rA, GPRC:$rB)>;
+def : Pat<(int_ppc_altivec_dststt GPRC:$rA, GPRC:$rB, imm:$STRM),
+          (DSTST 1, imm:$STRM, GPRC:$rA, GPRC:$rB)>;
+
 // Undef/Zero.
 def : Pat<(v16i8 (undef)), (v16i8 (IMPLICIT_DEF_VRRC))>;
 def : Pat<(v8i16 (undef)), (v8i16 (IMPLICIT_DEF_VRRC))>;