/// InstructionSelectBasicBlock - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
- virtual void InstructionSelectBasicBlock(SelectionDAG &DAG) {
- DEBUG(BB->dump());
- // Select target instructions for the DAG.
- DAG.setRoot(Select(DAG.getRoot()));
- CodeGenMap.clear();
- DAG.RemoveDeadNodes();
-
- // Emit machine code to BB.
- ScheduleAndEmitDAG(DAG);
- }
-
+ virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
+
virtual const char *getPassName() const {
return "PowerPC DAG->DAG Pattern Instruction Selection";
}
// Include the pieces autogenerated from the target description.
#include "PPC32GenDAGISel.inc"
+
+private:
+ SDOperand SelectDYNAMIC_STACKALLOC(SDOperand Op);
+ SDOperand SelectADD_PARTS(SDOperand Op);
+ SDOperand SelectSUB_PARTS(SDOperand Op);
+ SDOperand SelectSETCC(SDOperand Op);
+ SDOperand SelectCALL(SDOperand Op);
};
}
+/// InstructionSelectBasicBlock - This callback is invoked by
+/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
+void PPC32DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
+ DEBUG(BB->dump());
+
+ // The selection process is inherently a bottom-up recursive process (users
+ // select their uses before themselves). Given infinite stack space, we
+ // could just start selecting on the root and traverse the whole graph. In
+ // practice however, this causes us to run out of stack space on large basic
+ // blocks. To avoid this problem, select the entry node, then all its uses,
+ // iteratively instead of recursively.
+ std::vector<SDOperand> Worklist;
+ Worklist.push_back(DAG.getEntryNode());
+
+ // Note that we can do this in the PPC target (scanning forward across token
+ // chain edges) because no nodes ever get folded across these edges. On a
+ // target like X86 which supports load/modify/store operations, this would
+ // have to be more careful.
+ while (!Worklist.empty()) {
+ SDOperand Node = Worklist.back();
+ Worklist.pop_back();
+
+ // Chose from the least deep of the top two nodes.
+ if (!Worklist.empty() &&
+ Worklist.back().Val->getNodeDepth() < Node.Val->getNodeDepth())
+ std::swap(Worklist.back(), Node);
+
+ if ((Node.Val->getOpcode() >= ISD::BUILTIN_OP_END &&
+ Node.Val->getOpcode() < PPCISD::FIRST_NUMBER) ||
+ CodeGenMap.count(Node)) continue;
+
+ for (SDNode::use_iterator UI = Node.Val->use_begin(),
+ E = Node.Val->use_end(); UI != E; ++UI) {
+ // Scan the values. If this use has a value that is a token chain, add it
+ // to the worklist.
+ SDNode *User = *UI;
+ for (unsigned i = 0, e = User->getNumValues(); i != e; ++i)
+ if (User->getValueType(i) == MVT::Other) {
+ Worklist.push_back(SDOperand(User, i));
+ break;
+ }
+ }
+
+ // Finally, legalize this node.
+ Select(Node);
+ }
+
+ // Select target instructions for the DAG.
+ DAG.setRoot(Select(DAG.getRoot()));
+ CodeGenMap.clear();
+ DAG.RemoveDeadNodes();
+
+ // Emit machine code to BB.
+ ScheduleAndEmitDAG(DAG);
+}
/// getGlobalBaseReg - Output the instructions required to put the
/// base address to use for accessing globals into a register.
return false;
}
-// isRotateAndMask - Returns true if Mask and Shift can be folded in to a rotate
+// isRotateAndMask - Returns true if Mask and Shift can be folded into a rotate
// and mask opcode and mask operation.
static bool isRotateAndMask(SDNode *N, unsigned Mask, bool IsShiftMask,
unsigned &SH, unsigned &MB, unsigned &ME) {
LHS, getI32Imm(Lo16(Imm)));
return CurDAG->getTargetNode(U ? PPC::CMPLW : PPC::CMPW, MVT::i32,
LHS, Select(RHS));
+ } else if (LHS.getValueType() == MVT::f32) {
+ return CurDAG->getTargetNode(PPC::FCMPUS, MVT::i32, LHS, Select(RHS));
} else {
- return CurDAG->getTargetNode(PPC::FCMPU, MVT::i32, LHS, Select(RHS));
+ return CurDAG->getTargetNode(PPC::FCMPUD, MVT::i32, LHS, Select(RHS));
}
}
}
}
+SDOperand PPC32DAGToDAGISel::SelectDYNAMIC_STACKALLOC(SDOperand Op) {
+ SDNode *N = Op.Val;
+
+ // FIXME: We are currently ignoring the requested alignment for handling
+ // greater than the stack alignment. This will need to be revisited at some
+ // point. Align = N.getOperand(2);
+ if (!isa<ConstantSDNode>(N->getOperand(2)) ||
+ cast<ConstantSDNode>(N->getOperand(2))->getValue() != 0) {
+ std::cerr << "Cannot allocate stack object with greater alignment than"
+ << " the stack alignment yet!";
+ abort();
+ }
+ SDOperand Chain = Select(N->getOperand(0));
+ SDOperand Amt = Select(N->getOperand(1));
+
+ SDOperand R1Reg = CurDAG->getRegister(PPC::R1, MVT::i32);
+
+ SDOperand R1Val = CurDAG->getCopyFromReg(Chain, PPC::R1, MVT::i32);
+ Chain = R1Val.getValue(1);
+
+ // Subtract the amount (guaranteed to be a multiple of the stack alignment)
+ // from the stack pointer, giving us the result pointer.
+ SDOperand Result = CurDAG->getTargetNode(PPC::SUBF, MVT::i32, Amt, R1Val);
+
+ // Copy this result back into R1.
+ Chain = CurDAG->getNode(ISD::CopyToReg, MVT::Other, Chain, R1Reg, Result);
+
+ // Copy this result back out of R1 to make sure we're not using the stack
+ // space without decrementing the stack pointer.
+ Result = CurDAG->getCopyFromReg(Chain, PPC::R1, MVT::i32);
+
+ // Finally, replace the DYNAMIC_STACKALLOC with the copyfromreg.
+ CodeGenMap[Op.getValue(0)] = Result;
+ CodeGenMap[Op.getValue(1)] = Result.getValue(1);
+ return SDOperand(Result.Val, Op.ResNo);
+}
+
+SDOperand PPC32DAGToDAGISel::SelectADD_PARTS(SDOperand Op) {
+ SDNode *N = Op.Val;
+ SDOperand LHSL = Select(N->getOperand(0));
+ SDOperand LHSH = Select(N->getOperand(1));
+
+ unsigned Imm;
+ bool ME = false, ZE = false;
+ if (isIntImmediate(N->getOperand(3), Imm)) {
+ ME = (signed)Imm == -1;
+ ZE = Imm == 0;
+ }
+
+ std::vector<SDOperand> Result;
+ SDOperand CarryFromLo;
+ if (isIntImmediate(N->getOperand(2), Imm) &&
+ ((signed)Imm >= -32768 || (signed)Imm < 32768)) {
+ // Codegen the low 32 bits of the add. Interestingly, there is no
+ // shifted form of add immediate carrying.
+ CarryFromLo = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
+ LHSL, getI32Imm(Imm));
+ } else {
+ CarryFromLo = CurDAG->getTargetNode(PPC::ADDC, MVT::i32, MVT::Flag,
+ LHSL, Select(N->getOperand(2)));
+ }
+ CarryFromLo = CarryFromLo.getValue(1);
+
+ // Codegen the high 32 bits, adding zero, minus one, or the full value
+ // along with the carry flag produced by addc/addic.
+ SDOperand ResultHi;
+ if (ZE)
+ ResultHi = CurDAG->getTargetNode(PPC::ADDZE, MVT::i32, LHSH, CarryFromLo);
+ else if (ME)
+ ResultHi = CurDAG->getTargetNode(PPC::ADDME, MVT::i32, LHSH, CarryFromLo);
+ else
+ ResultHi = CurDAG->getTargetNode(PPC::ADDE, MVT::i32, LHSH,
+ Select(N->getOperand(3)), CarryFromLo);
+ Result.push_back(CarryFromLo.getValue(0));
+ Result.push_back(ResultHi);
+
+ CodeGenMap[Op.getValue(0)] = Result[0];
+ CodeGenMap[Op.getValue(1)] = Result[1];
+ return Result[Op.ResNo];
+}
+SDOperand PPC32DAGToDAGISel::SelectSUB_PARTS(SDOperand Op) {
+ SDNode *N = Op.Val;
+ SDOperand LHSL = Select(N->getOperand(0));
+ SDOperand LHSH = Select(N->getOperand(1));
+ SDOperand RHSL = Select(N->getOperand(2));
+ SDOperand RHSH = Select(N->getOperand(3));
+
+ std::vector<SDOperand> Result;
+ Result.push_back(CurDAG->getTargetNode(PPC::SUBFC, MVT::i32, MVT::Flag,
+ RHSL, LHSL));
+ Result.push_back(CurDAG->getTargetNode(PPC::SUBFE, MVT::i32, RHSH, LHSH,
+ Result[0].getValue(1)));
+ CodeGenMap[Op.getValue(0)] = Result[0];
+ CodeGenMap[Op.getValue(1)] = Result[1];
+ return Result[Op.ResNo];
+}
+
+SDOperand PPC32DAGToDAGISel::SelectSETCC(SDOperand Op) {
+ SDNode *N = Op.Val;
+ unsigned Imm;
+ ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
+ if (isIntImmediate(N->getOperand(1), Imm)) {
+ // We can codegen setcc op, imm very efficiently compared to a brcond.
+ // Check for those cases here.
+ // setcc op, 0
+ if (Imm == 0) {
+ SDOperand Op = Select(N->getOperand(0));
+ switch (CC) {
+ default: assert(0 && "Unhandled SetCC condition"); abort();
+ case ISD::SETEQ:
+ Op = CurDAG->getTargetNode(PPC::CNTLZW, MVT::i32, Op);
+ CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Op, getI32Imm(27),
+ getI32Imm(5), getI32Imm(31));
+ break;
+ case ISD::SETNE: {
+ SDOperand AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
+ Op, getI32Imm(~0U));
+ CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op, AD.getValue(1));
+ break;
+ }
+ case ISD::SETLT:
+ CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Op, getI32Imm(1),
+ getI32Imm(31), getI32Imm(31));
+ break;
+ case ISD::SETGT: {
+ SDOperand T = CurDAG->getTargetNode(PPC::NEG, MVT::i32, Op);
+ T = CurDAG->getTargetNode(PPC::ANDC, MVT::i32, T, Op);;
+ CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, T, getI32Imm(1),
+ getI32Imm(31), getI32Imm(31));
+ break;
+ }
+ }
+ return SDOperand(N, 0);
+ } else if (Imm == ~0U) { // setcc op, -1
+ SDOperand Op = Select(N->getOperand(0));
+ switch (CC) {
+ default: assert(0 && "Unhandled SetCC condition"); abort();
+ case ISD::SETEQ:
+ Op = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
+ Op, getI32Imm(1));
+ CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
+ CurDAG->getTargetNode(PPC::LI, MVT::i32,
+ getI32Imm(0)),
+ Op.getValue(1));
+ break;
+ case ISD::SETNE: {
+ Op = CurDAG->getTargetNode(PPC::NOR, MVT::i32, Op, Op);
+ SDOperand AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
+ Op, getI32Imm(~0U));
+ CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op, AD.getValue(1));
+ break;
+ }
+ case ISD::SETLT: {
+ SDOperand AD = CurDAG->getTargetNode(PPC::ADDI, MVT::i32, Op,
+ getI32Imm(1));
+ SDOperand AN = CurDAG->getTargetNode(PPC::AND, MVT::i32, AD, Op);
+ CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, AN, getI32Imm(1),
+ getI32Imm(31), getI32Imm(31));
+ break;
+ }
+ case ISD::SETGT:
+ Op = CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Op, getI32Imm(1),
+ getI32Imm(31), getI32Imm(31));
+ CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op, getI32Imm(1));
+ break;
+ }
+ return SDOperand(N, 0);
+ }
+ }
+
+ bool Inv;
+ unsigned Idx = getCRIdxForSetCC(CC, Inv);
+ SDOperand CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC);
+ SDOperand IntCR;
+
+ // Force the ccreg into CR7.
+ SDOperand CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
+
+ std::vector<MVT::ValueType> VTs;
+ VTs.push_back(MVT::Other);
+ VTs.push_back(MVT::Flag); // NONSTANDARD CopyToReg node: defines a flag
+ std::vector<SDOperand> Ops;
+ Ops.push_back(CurDAG->getEntryNode());
+ Ops.push_back(CR7Reg);
+ Ops.push_back(CCReg);
+ CCReg = CurDAG->getNode(ISD::CopyToReg, VTs, Ops).getValue(1);
+
+ if (TLI.getTargetMachine().getSubtarget<PPCSubtarget>().isGigaProcessor())
+ IntCR = CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32, CR7Reg, CCReg);
+ else
+ IntCR = CurDAG->getTargetNode(PPC::MFCR, MVT::i32, CCReg);
+
+ if (!Inv) {
+ CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, IntCR,
+ getI32Imm(32-(3-Idx)), getI32Imm(31), getI32Imm(31));
+ } else {
+ SDOperand Tmp =
+ CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, IntCR,
+ getI32Imm(32-(3-Idx)), getI32Imm(31),getI32Imm(31));
+ CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1));
+ }
+
+ return SDOperand(N, 0);
+}
+
+SDOperand PPC32DAGToDAGISel::SelectCALL(SDOperand Op) {
+ SDNode *N = Op.Val;
+ SDOperand Chain = Select(N->getOperand(0));
+
+ unsigned CallOpcode;
+ std::vector<SDOperand> CallOperands;
+
+ if (GlobalAddressSDNode *GASD =
+ dyn_cast<GlobalAddressSDNode>(N->getOperand(1))) {
+ CallOpcode = PPC::CALLpcrel;
+ CallOperands.push_back(CurDAG->getTargetGlobalAddress(GASD->getGlobal(),
+ MVT::i32));
+ } else if (ExternalSymbolSDNode *ESSDN =
+ dyn_cast<ExternalSymbolSDNode>(N->getOperand(1))) {
+ CallOpcode = PPC::CALLpcrel;
+ CallOperands.push_back(N->getOperand(1));
+ } else {
+ // Copy the callee address into the CTR register.
+ SDOperand Callee = Select(N->getOperand(1));
+ Chain = CurDAG->getTargetNode(PPC::MTCTR, MVT::Other, Callee, Chain);
+
+ // Copy the callee address into R12 on darwin.
+ SDOperand R12 = CurDAG->getRegister(PPC::R12, MVT::i32);
+ Chain = CurDAG->getNode(ISD::CopyToReg, MVT::Other, Chain, R12, Callee);
+
+ CallOperands.push_back(getI32Imm(20)); // Information to encode indcall
+ CallOperands.push_back(getI32Imm(0)); // Information to encode indcall
+ CallOperands.push_back(R12);
+ CallOpcode = PPC::CALLindirect;
+ }
+
+ unsigned GPR_idx = 0, FPR_idx = 0;
+ static const unsigned GPR[] = {
+ PPC::R3, PPC::R4, PPC::R5, PPC::R6,
+ PPC::R7, PPC::R8, PPC::R9, PPC::R10,
+ };
+ static const unsigned FPR[] = {
+ PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
+ PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
+ };
+
+ SDOperand InFlag; // Null incoming flag value.
+
+ for (unsigned i = 2, e = N->getNumOperands(); i != e; ++i) {
+ unsigned DestReg = 0;
+ MVT::ValueType RegTy = N->getOperand(i).getValueType();
+ if (RegTy == MVT::i32) {
+ assert(GPR_idx < 8 && "Too many int args");
+ DestReg = GPR[GPR_idx++];
+ } else {
+ assert(MVT::isFloatingPoint(N->getOperand(i).getValueType()) &&
+ "Unpromoted integer arg?");
+ assert(FPR_idx < 13 && "Too many fp args");
+ DestReg = FPR[FPR_idx++];
+ }
+
+ if (N->getOperand(i).getOpcode() != ISD::UNDEF) {
+ SDOperand Val = Select(N->getOperand(i));
+ Chain = CurDAG->getCopyToReg(Chain, DestReg, Val, InFlag);
+ InFlag = Chain.getValue(1);
+ CallOperands.push_back(CurDAG->getRegister(DestReg, RegTy));
+ }
+ }
+
+ // Finally, once everything is in registers to pass to the call, emit the
+ // call itself.
+ if (InFlag.Val)
+ CallOperands.push_back(InFlag); // Strong dep on register copies.
+ else
+ CallOperands.push_back(Chain); // Weak dep on whatever occurs before
+ Chain = CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag,
+ CallOperands);
+
+ std::vector<SDOperand> CallResults;
+
+ // If the call has results, copy the values out of the ret val registers.
+ switch (N->getValueType(0)) {
+ default: assert(0 && "Unexpected ret value!");
+ case MVT::Other: break;
+ case MVT::i32:
+ if (N->getValueType(1) == MVT::i32) {
+ Chain = CurDAG->getCopyFromReg(Chain, PPC::R4, MVT::i32,
+ Chain.getValue(1)).getValue(1);
+ CallResults.push_back(Chain.getValue(0));
+ Chain = CurDAG->getCopyFromReg(Chain, PPC::R3, MVT::i32,
+ Chain.getValue(2)).getValue(1);
+ CallResults.push_back(Chain.getValue(0));
+ } else {
+ Chain = CurDAG->getCopyFromReg(Chain, PPC::R3, MVT::i32,
+ Chain.getValue(1)).getValue(1);
+ CallResults.push_back(Chain.getValue(0));
+ }
+ break;
+ case MVT::f32:
+ case MVT::f64:
+ Chain = CurDAG->getCopyFromReg(Chain, PPC::F1, N->getValueType(0),
+ Chain.getValue(1)).getValue(1);
+ CallResults.push_back(Chain.getValue(0));
+ break;
+ }
+
+ CallResults.push_back(Chain);
+ for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
+ CodeGenMap[Op.getValue(i)] = CallResults[i];
+ return CallResults[Op.ResNo];
+}
+
// Select - Convert the specified operand from a target-independent to a
// target-specific node if it hasn't already been changed.
SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
N->getOpcode() < PPCISD::FIRST_NUMBER)
return Op; // Already selected.
+
+ // If this has already been converted, use it.
+ std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
+ if (CGMI != CodeGenMap.end()) return CGMI->second;
switch (N->getOpcode()) {
default: break;
+ case ISD::DYNAMIC_STACKALLOC: return SelectDYNAMIC_STACKALLOC(Op);
+ case ISD::ADD_PARTS: return SelectADD_PARTS(Op);
+ case ISD::SUB_PARTS: return SelectSUB_PARTS(Op);
+ case ISD::SETCC: return SelectSETCC(Op);
+ case ISD::CALL: return SelectCALL(Op);
+ case ISD::TAILCALL: return SelectCALL(Op);
+
case ISD::TokenFactor: {
SDOperand New;
if (N->getNumOperands() == 2) {
New = CurDAG->getNode(ISD::TokenFactor, MVT::Other, Ops);
}
- if (New.Val != N) {
- CurDAG->ReplaceAllUsesWith(Op, New);
- N = New.Val;
- }
- return SDOperand(N, 0);
+ CodeGenMap[Op] = New;
+ return New;
}
case ISD::CopyFromReg: {
SDOperand Chain = Select(N->getOperand(0));
SDOperand Chain = Select(N->getOperand(0));
SDOperand Reg = N->getOperand(1);
SDOperand Val = Select(N->getOperand(2));
- if (Chain != N->getOperand(0) || Val != N->getOperand(2)) {
- SDOperand New = CurDAG->getNode(ISD::CopyToReg, MVT::Other,
- Chain, Reg, Val);
- CurDAG->ReplaceAllUsesWith(Op, New);
- N = New.Val;
- }
- return SDOperand(N, 0);
+ SDOperand New = CurDAG->getNode(ISD::CopyToReg, MVT::Other,
+ Chain, Reg, Val);
+ CodeGenMap[Op] = New;
+ return New;
}
case ISD::UNDEF:
if (N->getValueType(0) == MVT::i32)
CurDAG->SelectNodeTo(N, PPC::IMPLICIT_DEF_GPR, MVT::i32);
- else
- CurDAG->SelectNodeTo(N, PPC::IMPLICIT_DEF_FP, N->getValueType(0));
+ else if (N->getValueType(0) == MVT::f32)
+ CurDAG->SelectNodeTo(N, PPC::IMPLICIT_DEF_F4, MVT::f32);
+ else
+ CurDAG->SelectNodeTo(N, PPC::IMPLICIT_DEF_F8, MVT::f64);
return SDOperand(N, 0);
case ISD::FrameIndex: {
int FI = cast<FrameIndexSDNode>(N)->getIndex();
CurDAG->SelectNodeTo(N, PPC::LA, MVT::i32, Tmp, GA);
return SDOperand(N, 0);
}
- case ISD::DYNAMIC_STACKALLOC: {
- // FIXME: We are currently ignoring the requested alignment for handling
- // greater than the stack alignment. This will need to be revisited at some
- // point. Align = N.getOperand(2);
- if (!isa<ConstantSDNode>(N->getOperand(2)) ||
- cast<ConstantSDNode>(N->getOperand(2))->getValue() != 0) {
- std::cerr << "Cannot allocate stack object with greater alignment than"
- << " the stack alignment yet!";
- abort();
- }
- SDOperand Chain = Select(N->getOperand(0));
- SDOperand Amt = Select(N->getOperand(1));
-
- SDOperand R1Reg = CurDAG->getRegister(PPC::R1, MVT::i32);
- SDOperand R1Val = CurDAG->getCopyFromReg(Chain, PPC::R1, MVT::i32);
- Chain = R1Val.getValue(1);
+ case PPCISD::FSEL: {
+ SDOperand Comparison = Select(N->getOperand(0));
+ // Extend the comparison to 64-bits.
+ if (Comparison.getValueType() == MVT::f32)
+ Comparison = CurDAG->getTargetNode(PPC::FMRSD, MVT::f64, Comparison);
- // Subtract the amount (guaranteed to be a multiple of the stack alignment)
- // from the stack pointer, giving us the result pointer.
- SDOperand Result = CurDAG->getTargetNode(PPC::SUBF, MVT::i32, Amt, R1Val);
-
- // Copy this result back into R1.
- Chain = CurDAG->getNode(ISD::CopyToReg, MVT::Other, Chain, R1Reg, Result);
-
- // Copy this result back out of R1 to make sure we're not using the stack
- // space without decrementing the stack pointer.
- Result = CurDAG->getCopyFromReg(Chain, PPC::R1, MVT::i32);
-
- // Finally, replace the DYNAMIC_STACKALLOC with the copyfromreg.
- CurDAG->ReplaceAllUsesWith(N, Result.Val);
- return SDOperand(Result.Val, Op.ResNo);
- }
- case PPCISD::FSEL:
- CurDAG->SelectNodeTo(N, PPC::FSEL, N->getValueType(0),
- Select(N->getOperand(0)),
- Select(N->getOperand(1)),
- Select(N->getOperand(2)));
+ unsigned Opc = N->getValueType(0) == MVT::f32 ? PPC::FSELS : PPC::FSELD;
+ CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), Comparison,
+ Select(N->getOperand(1)), Select(N->getOperand(2)));
return SDOperand(N, 0);
+ }
case PPCISD::FCFID:
CurDAG->SelectNodeTo(N, PPC::FCFID, N->getValueType(0),
Select(N->getOperand(0)));
CurDAG->SelectNodeTo(N, PPC::FCTIWZ, N->getValueType(0),
Select(N->getOperand(0)));
return SDOperand(N, 0);
- case ISD::ADD: {
+ case ISD::FADD: {
MVT::ValueType Ty = N->getValueType(0);
- if (Ty == MVT::i32) {
- if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0), N->getOperand(1),
- PPC::ADDIS, PPC::ADDI, true)) {
- CurDAG->ReplaceAllUsesWith(Op, SDOperand(I, 0));
- N = I;
- } else {
- CurDAG->SelectNodeTo(N, PPC::ADD, MVT::i32, Select(N->getOperand(0)),
- Select(N->getOperand(1)));
- }
- return SDOperand(N, 0);
- }
-
if (!NoExcessFPPrecision) { // Match FMA ops
- if (N->getOperand(0).getOpcode() == ISD::MUL &&
+ if (N->getOperand(0).getOpcode() == ISD::FMUL &&
N->getOperand(0).Val->hasOneUse()) {
++FusedFP; // Statistic
CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FMADD : PPC::FMADDS, Ty,
Select(N->getOperand(0).getOperand(1)),
Select(N->getOperand(1)));
return SDOperand(N, 0);
- } else if (N->getOperand(1).getOpcode() == ISD::MUL &&
+ } else if (N->getOperand(1).getOpcode() == ISD::FMUL &&
N->getOperand(1).hasOneUse()) {
++FusedFP; // Statistic
CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FMADD : PPC::FMADDS, Ty,
Select(N->getOperand(0)), Select(N->getOperand(1)));
return SDOperand(N, 0);
}
- case ISD::SUB: {
+ case ISD::FSUB: {
MVT::ValueType Ty = N->getValueType(0);
- if (Ty == MVT::i32) {
- unsigned Imm;
- if (isIntImmediate(N->getOperand(0), Imm) && isInt16(Imm)) {
- if (0 == Imm)
- CurDAG->SelectNodeTo(N, PPC::NEG, Ty, Select(N->getOperand(1)));
- else
- CurDAG->SelectNodeTo(N, PPC::SUBFIC, Ty, Select(N->getOperand(1)),
- getI32Imm(Lo16(Imm)));
- return SDOperand(N, 0);
- }
- if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0), N->getOperand(1),
- PPC::ADDIS, PPC::ADDI, true, true)) {
- CurDAG->ReplaceAllUsesWith(Op, SDOperand(I, 0));
- N = I;
- } else {
- CurDAG->SelectNodeTo(N, PPC::SUBF, Ty, Select(N->getOperand(1)),
- Select(N->getOperand(0)));
- }
- return SDOperand(N, 0);
- }
if (!NoExcessFPPrecision) { // Match FMA ops
- if (N->getOperand(0).getOpcode() == ISD::MUL &&
+ if (N->getOperand(0).getOpcode() == ISD::FMUL &&
N->getOperand(0).Val->hasOneUse()) {
++FusedFP; // Statistic
CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FMSUB : PPC::FMSUBS, Ty,
Select(N->getOperand(0).getOperand(1)),
Select(N->getOperand(1)));
return SDOperand(N, 0);
- } else if (N->getOperand(1).getOpcode() == ISD::MUL &&
+ } else if (N->getOperand(1).getOpcode() == ISD::FMUL &&
N->getOperand(1).Val->hasOneUse()) {
++FusedFP; // Statistic
CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FNMSUB : PPC::FNMSUBS, Ty,
Select(N->getOperand(1)));
return SDOperand(N, 0);
}
- case ISD::MUL: {
- unsigned Imm, Opc;
- if (isIntImmediate(N->getOperand(1), Imm) && isInt16(Imm)) {
- CurDAG->SelectNodeTo(N, PPC::MULLI, MVT::i32,
- Select(N->getOperand(0)), getI32Imm(Lo16(Imm)));
- return SDOperand(N, 0);
- }
- switch (N->getValueType(0)) {
- default: assert(0 && "Unhandled multiply type!");
- case MVT::i32: Opc = PPC::MULLW; break;
- case MVT::f32: Opc = PPC::FMULS; break;
- case MVT::f64: Opc = PPC::FMUL; break;
- }
- CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), Select(N->getOperand(0)),
- Select(N->getOperand(1)));
- return SDOperand(N, 0);
- }
case ISD::SDIV: {
unsigned Imm;
if (isIntImmediate(N->getOperand(1), Imm)) {
return SDOperand(N, 0);
} else if (Imm) {
SDOperand Result = Select(BuildSDIVSequence(N));
- assert(Result.ResNo == 0);
- CurDAG->ReplaceAllUsesWith(Op, Result);
- N = Result.Val;
- return SDOperand(N, 0);
+ CodeGenMap[Op] = Result;
+ return Result;
}
}
- unsigned Opc;
- switch (N->getValueType(0)) {
- default: assert(0 && "Unknown type to ISD::SDIV");
- case MVT::i32: Opc = PPC::DIVW; break;
- case MVT::f32: Opc = PPC::FDIVS; break;
- case MVT::f64: Opc = PPC::FDIV; break;
- }
- CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), Select(N->getOperand(0)),
- Select(N->getOperand(1)));
- return SDOperand(N, 0);
+ // Other cases are autogenerated.
+ break;
}
case ISD::UDIV: {
// If this is a divide by constant, we can emit code using some magic
unsigned Imm;
if (isIntImmediate(N->getOperand(1), Imm) && Imm) {
SDOperand Result = Select(BuildUDIVSequence(N));
- assert(Result.ResNo == 0);
- CurDAG->ReplaceAllUsesWith(Op, Result);
- N = Result.Val;
- return SDOperand(N, 0);
+ CodeGenMap[Op] = Result;
+ return Result;
}
- CurDAG->SelectNodeTo(N, PPC::DIVWU, MVT::i32, Select(N->getOperand(0)),
- Select(N->getOperand(1)));
- return SDOperand(N, 0);
+ // Other cases are autogenerated.
+ break;
}
case ISD::AND: {
unsigned Imm;
getI32Imm(MB), getI32Imm(ME));
return SDOperand(N, 0);
}
- // Finally, check for the case where we are being asked to select
- // and (not(a), b) or and (a, not(b)) which can be selected as andc.
- if (isOprNot(N->getOperand(0).Val))
- CurDAG->SelectNodeTo(N, PPC::ANDC, MVT::i32, Select(N->getOperand(1)),
- Select(N->getOperand(0).getOperand(0)));
- else if (isOprNot(N->getOperand(1).Val))
- CurDAG->SelectNodeTo(N, PPC::ANDC, MVT::i32, Select(N->getOperand(0)),
- Select(N->getOperand(1).getOperand(0)));
- else
- CurDAG->SelectNodeTo(N, PPC::AND, MVT::i32, Select(N->getOperand(0)),
- Select(N->getOperand(1)));
- return SDOperand(N, 0);
+
+ // Other cases are autogenerated.
+ break;
}
case ISD::OR:
- if (SDNode *I = SelectBitfieldInsert(N)) {
- CurDAG->ReplaceAllUsesWith(Op, SDOperand(I, 0));
- N = I;
- return SDOperand(N, 0);
- }
+ if (SDNode *I = SelectBitfieldInsert(N))
+ return CodeGenMap[Op] = SDOperand(I, 0);
+
if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0),
N->getOperand(1),
- PPC::ORIS, PPC::ORI)) {
- CurDAG->ReplaceAllUsesWith(Op, SDOperand(I, 0));
- N = I;
- return SDOperand(N, 0);
- }
- // Finally, check for the case where we are being asked to select
- // 'or (not(a), b)' or 'or (a, not(b))' which can be selected as orc.
- if (isOprNot(N->getOperand(0).Val))
- CurDAG->SelectNodeTo(N, PPC::ORC, MVT::i32, Select(N->getOperand(1)),
- Select(N->getOperand(0).getOperand(0)));
- else if (isOprNot(N->getOperand(1).Val))
- CurDAG->SelectNodeTo(N, PPC::ORC, MVT::i32, Select(N->getOperand(0)),
- Select(N->getOperand(1).getOperand(0)));
- else
- CurDAG->SelectNodeTo(N, PPC::OR, MVT::i32, Select(N->getOperand(0)),
- Select(N->getOperand(1)));
- return SDOperand(N, 0);
+ PPC::ORIS, PPC::ORI))
+ return CodeGenMap[Op] = SDOperand(I, 0);
+
+ // Other cases are autogenerated.
+ break;
case ISD::SHL: {
unsigned Imm, SH, MB, ME;
if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
}
case ISD::SRA: {
unsigned Imm, SH, MB, ME;
- if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
+ if (0 &&isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
isRotateAndMask(N, Imm, true, SH, MB, ME))
CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32,
Select(N->getOperand(0).getOperand(0)),
Select(N->getOperand(1)));
return SDOperand(N, 0);
}
- case ISD::FABS:
- CurDAG->SelectNodeTo(N, PPC::FABS, N->getValueType(0),
- Select(N->getOperand(0)));
+ case ISD::FMUL: {
+ unsigned Opc = N->getValueType(0) == MVT::f32 ? PPC::FMULS : PPC::FMUL;
+ CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), Select(N->getOperand(0)),
+ Select(N->getOperand(1)));
return SDOperand(N, 0);
- case ISD::FP_EXTEND:
- assert(MVT::f64 == N->getValueType(0) &&
- MVT::f32 == N->getOperand(0).getValueType() && "Illegal FP_EXTEND");
- // We need to emit an FMR to make sure that the result has the right value
- // type.
- CurDAG->SelectNodeTo(N, PPC::FMR, MVT::f64, Select(N->getOperand(0)));
+ }
+ case ISD::FDIV: {
+ unsigned Opc = N->getValueType(0) == MVT::f32 ? PPC::FDIVS : PPC::FDIV;
+ CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), Select(N->getOperand(0)),
+ Select(N->getOperand(1)));
return SDOperand(N, 0);
- case ISD::FP_ROUND:
- assert(MVT::f32 == N->getValueType(0) &&
- MVT::f64 == N->getOperand(0).getValueType() && "Illegal FP_ROUND");
- CurDAG->SelectNodeTo(N, PPC::FRSP, MVT::f32, Select(N->getOperand(0)));
+ }
+ case ISD::FABS:
+ if (N->getValueType(0) == MVT::f32)
+ CurDAG->SelectNodeTo(N, PPC::FABSS, MVT::f32, Select(N->getOperand(0)));
+ else
+ CurDAG->SelectNodeTo(N, PPC::FABSD, MVT::f64, Select(N->getOperand(0)));
return SDOperand(N, 0);
case ISD::FNEG: {
SDOperand Val = Select(N->getOperand(0));
unsigned Opc;
switch (Val.isTargetOpcode() ? Val.getTargetOpcode() : 0) {
default: Opc = 0; break;
- case PPC::FABS: Opc = PPC::FNABS; break;
+ case PPC::FABSS: Opc = PPC::FNABSS; break;
+ case PPC::FABSD: Opc = PPC::FNABSD; break;
case PPC::FMADD: Opc = PPC::FNMADD; break;
case PPC::FMADDS: Opc = PPC::FNMADDS; break;
case PPC::FMSUB: Opc = PPC::FNMSUB; break;
// inverted opcode and the original instruction's operands. Otherwise,
// fall through and generate a fneg instruction.
if (Opc) {
- if (PPC::FNABS == Opc)
+ if (Opc == PPC::FNABSS || Opc == PPC::FNABSD)
CurDAG->SelectNodeTo(N, Opc, Ty, Val.getOperand(0));
else
CurDAG->SelectNodeTo(N, Opc, Ty, Val.getOperand(0),
return SDOperand(N, 0);
}
}
- CurDAG->SelectNodeTo(N, PPC::FNEG, Ty, Val);
+ if (Ty == MVT::f32)
+ CurDAG->SelectNodeTo(N, PPC::FNEGS, MVT::f32, Val);
+ else
+ CurDAG->SelectNodeTo(N, PPC::FNEGD, MVT::f64, Val);
return SDOperand(N, 0);
}
case ISD::FSQRT: {
Select(N->getOperand(0)));
return SDOperand(N, 0);
}
-
- case ISD::ADD_PARTS: {
- SDOperand LHSL = Select(N->getOperand(0));
- SDOperand LHSH = Select(N->getOperand(1));
-
- unsigned Imm;
- bool ME = false, ZE = false;
- if (isIntImmediate(N->getOperand(3), Imm)) {
- ME = (signed)Imm == -1;
- ZE = Imm == 0;
- }
-
- std::vector<SDOperand> Result;
- SDOperand CarryFromLo;
- if (isIntImmediate(N->getOperand(2), Imm) &&
- ((signed)Imm >= -32768 || (signed)Imm < 32768)) {
- // Codegen the low 32 bits of the add. Interestingly, there is no
- // shifted form of add immediate carrying.
- CarryFromLo = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
- LHSL, getI32Imm(Imm));
- } else {
- CarryFromLo = CurDAG->getTargetNode(PPC::ADDC, MVT::i32, MVT::Flag,
- LHSL, Select(N->getOperand(2)));
- }
- CarryFromLo = CarryFromLo.getValue(1);
-
- // Codegen the high 32 bits, adding zero, minus one, or the full value
- // along with the carry flag produced by addc/addic.
- SDOperand ResultHi;
- if (ZE)
- ResultHi = CurDAG->getTargetNode(PPC::ADDZE, MVT::i32, LHSH, CarryFromLo);
- else if (ME)
- ResultHi = CurDAG->getTargetNode(PPC::ADDME, MVT::i32, LHSH, CarryFromLo);
- else
- ResultHi = CurDAG->getTargetNode(PPC::ADDE, MVT::i32, LHSH,
- Select(N->getOperand(3)), CarryFromLo);
- Result.push_back(CarryFromLo.getValue(0));
- Result.push_back(ResultHi);
- CurDAG->ReplaceAllUsesWith(N, Result);
- return Result[Op.ResNo];
- }
- case ISD::SUB_PARTS: {
- SDOperand LHSL = Select(N->getOperand(0));
- SDOperand LHSH = Select(N->getOperand(1));
- SDOperand RHSL = Select(N->getOperand(2));
- SDOperand RHSH = Select(N->getOperand(3));
-
- std::vector<SDOperand> Result;
- Result.push_back(CurDAG->getTargetNode(PPC::SUBFC, MVT::i32, MVT::Flag,
- RHSL, LHSL));
- Result.push_back(CurDAG->getTargetNode(PPC::SUBFE, MVT::i32, RHSH, LHSH,
- Result[0].getValue(1)));
- CurDAG->ReplaceAllUsesWith(N, Result);
- return Result[Op.ResNo];
- }
-
case ISD::LOAD:
case ISD::EXTLOAD:
case ISD::ZEXTLOAD:
case MVT::f64: Opc = isIdx ? PPC::LFDX : PPC::LFD; break;
}
- CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
- Op1, Op2, Select(N->getOperand(0)));
- return SDOperand(N, Op.ResNo);
+ // If this is an f32 -> f64 load, emit the f32 load, then use an 'extending
+ // copy'.
+ if (TypeBeingLoaded != MVT::f32 || N->getOpcode() == ISD::LOAD) {
+ CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
+ Op1, Op2, Select(N->getOperand(0)));
+ return SDOperand(N, Op.ResNo);
+ } else {
+ std::vector<SDOperand> Ops;
+ Ops.push_back(Op1);
+ Ops.push_back(Op2);
+ Ops.push_back(Select(N->getOperand(0)));
+ SDOperand Res = CurDAG->getTargetNode(Opc, MVT::f32, MVT::Other, Ops);
+ SDOperand Ext = CurDAG->getTargetNode(PPC::FMRSD, MVT::f64, Res);
+ CodeGenMap[Op.getValue(0)] = Ext;
+ CodeGenMap[Op.getValue(1)] = Res.getValue(1);
+ if (Op.ResNo)
+ return Res.getValue(1);
+ else
+ return Ext;
+ }
}
-
case ISD::TRUNCSTORE:
case ISD::STORE: {
SDOperand AddrOp1, AddrOp2;
return SDOperand(N, 0);
}
- case ISD::SETCC: {
- unsigned Imm;
- ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
- if (isIntImmediate(N->getOperand(1), Imm)) {
- // We can codegen setcc op, imm very efficiently compared to a brcond.
- // Check for those cases here.
- // setcc op, 0
- if (Imm == 0) {
- SDOperand Op = Select(N->getOperand(0));
- switch (CC) {
- default: assert(0 && "Unhandled SetCC condition"); abort();
- case ISD::SETEQ:
- Op = CurDAG->getTargetNode(PPC::CNTLZW, MVT::i32, Op);
- CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Op, getI32Imm(27),
- getI32Imm(5), getI32Imm(31));
- break;
- case ISD::SETNE: {
- SDOperand AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
- Op, getI32Imm(~0U));
- CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op, AD.getValue(1));
- break;
- }
- case ISD::SETLT:
- CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Op, getI32Imm(1),
- getI32Imm(31), getI32Imm(31));
- break;
- case ISD::SETGT: {
- SDOperand T = CurDAG->getTargetNode(PPC::NEG, MVT::i32, Op);
- T = CurDAG->getTargetNode(PPC::ANDC, MVT::i32, T, Op);;
- CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, T, getI32Imm(1),
- getI32Imm(31), getI32Imm(31));
- break;
- }
- }
- return SDOperand(N, 0);
- } else if (Imm == ~0U) { // setcc op, -1
- SDOperand Op = Select(N->getOperand(0));
- switch (CC) {
- default: assert(0 && "Unhandled SetCC condition"); abort();
- case ISD::SETEQ:
- Op = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
- Op, getI32Imm(1));
- CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
- CurDAG->getTargetNode(PPC::LI, MVT::i32,
- getI32Imm(0)),
- Op.getValue(1));
- break;
- case ISD::SETNE: {
- Op = CurDAG->getTargetNode(PPC::NOR, MVT::i32, Op, Op);
- SDOperand AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
- Op, getI32Imm(~0U));
- CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op, AD.getValue(1));
- break;
- }
- case ISD::SETLT: {
- SDOperand AD = CurDAG->getTargetNode(PPC::ADDI, MVT::i32, Op,
- getI32Imm(1));
- SDOperand AN = CurDAG->getTargetNode(PPC::AND, MVT::i32, AD, Op);
- CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, AN, getI32Imm(1),
- getI32Imm(31), getI32Imm(31));
- break;
- }
- case ISD::SETGT:
- Op = CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Op, getI32Imm(1),
- getI32Imm(31), getI32Imm(31));
- CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op, getI32Imm(1));
- break;
- }
- return SDOperand(N, 0);
- }
- }
-
- bool Inv;
- unsigned Idx = getCRIdxForSetCC(CC, Inv);
- SDOperand CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC);
- SDOperand IntCR;
-
- // Force the ccreg into CR7.
- SDOperand CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
-
- std::vector<MVT::ValueType> VTs;
- VTs.push_back(MVT::Other);
- VTs.push_back(MVT::Flag); // NONSTANDARD CopyToReg node: defines a flag
- std::vector<SDOperand> Ops;
- Ops.push_back(CurDAG->getEntryNode());
- Ops.push_back(CR7Reg);
- Ops.push_back(CCReg);
- CCReg = CurDAG->getNode(ISD::CopyToReg, VTs, Ops).getValue(1);
-
- if (TLI.getTargetMachine().getSubtarget<PPCSubtarget>().isGigaProcessor())
- IntCR = CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32, CR7Reg, CCReg);
- else
- IntCR = CurDAG->getTargetNode(PPC::MFCR, MVT::i32, CCReg);
-
- if (!Inv) {
- CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, IntCR,
- getI32Imm(32-(3-Idx)), getI32Imm(31), getI32Imm(31));
- } else {
- SDOperand Tmp =
- CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, IntCR,
- getI32Imm(32-(3-Idx)), getI32Imm(31),getI32Imm(31));
- CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1));
- }
-
- return SDOperand(N, 0);
- }
-
case ISD::SELECT_CC: {
ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
unsigned BROpc = getBCCForSetCC(CC);
bool isFP = MVT::isFloatingPoint(N->getValueType(0));
- unsigned SelectCCOp = isFP ? PPC::SELECT_CC_FP : PPC::SELECT_CC_Int;
+ unsigned SelectCCOp;
+ if (MVT::isInteger(N->getValueType(0)))
+ SelectCCOp = PPC::SELECT_CC_Int;
+ else if (N->getValueType(0) == MVT::f32)
+ SelectCCOp = PPC::SELECT_CC_F4;
+ else
+ SelectCCOp = PPC::SELECT_CC_F8;
CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), CCReg,
Select(N->getOperand(2)), Select(N->getOperand(3)),
getI32Imm(BROpc));
getI32Imm(Amt), Select(N->getOperand(0)));
return SDOperand(N, 0);
}
- case ISD::CALL:
- case ISD::TAILCALL: {
- SDOperand Chain = Select(N->getOperand(0));
-
- unsigned CallOpcode;
- std::vector<SDOperand> CallOperands;
-
- if (GlobalAddressSDNode *GASD =
- dyn_cast<GlobalAddressSDNode>(N->getOperand(1))) {
- CallOpcode = PPC::CALLpcrel;
- CallOperands.push_back(CurDAG->getTargetGlobalAddress(GASD->getGlobal(),
- MVT::i32));
- } else if (ExternalSymbolSDNode *ESSDN =
- dyn_cast<ExternalSymbolSDNode>(N->getOperand(1))) {
- CallOpcode = PPC::CALLpcrel;
- CallOperands.push_back(N->getOperand(1));
- } else {
- // Copy the callee address into the CTR register.
- SDOperand Callee = Select(N->getOperand(1));
- Chain = CurDAG->getTargetNode(PPC::MTCTR, MVT::Other, Callee, Chain);
-
- // Copy the callee address into R12 on darwin.
- SDOperand R12 = CurDAG->getRegister(PPC::R12, MVT::i32);
- Chain = CurDAG->getNode(ISD::CopyToReg, MVT::Other, Chain, R12, Callee);
-
- CallOperands.push_back(getI32Imm(20)); // Information to encode indcall
- CallOperands.push_back(getI32Imm(0)); // Information to encode indcall
- CallOperands.push_back(R12);
- CallOpcode = PPC::CALLindirect;
- }
-
- unsigned GPR_idx = 0, FPR_idx = 0;
- static const unsigned GPR[] = {
- PPC::R3, PPC::R4, PPC::R5, PPC::R6,
- PPC::R7, PPC::R8, PPC::R9, PPC::R10,
- };
- static const unsigned FPR[] = {
- PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
- PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
- };
-
- SDOperand InFlag; // Null incoming flag value.
-
- for (unsigned i = 2, e = N->getNumOperands(); i != e; ++i) {
- unsigned DestReg = 0;
- MVT::ValueType RegTy = N->getOperand(i).getValueType();
- if (RegTy == MVT::i32) {
- assert(GPR_idx < 8 && "Too many int args");
- DestReg = GPR[GPR_idx++];
- } else {
- assert(MVT::isFloatingPoint(N->getOperand(i).getValueType()) &&
- "Unpromoted integer arg?");
- assert(FPR_idx < 13 && "Too many fp args");
- DestReg = FPR[FPR_idx++];
- }
-
- if (N->getOperand(i).getOpcode() != ISD::UNDEF) {
- SDOperand Val = Select(N->getOperand(i));
- Chain = CurDAG->getCopyToReg(Chain, DestReg, Val, InFlag);
- InFlag = Chain.getValue(1);
- CallOperands.push_back(CurDAG->getRegister(DestReg, RegTy));
- }
- }
-
- // Finally, once everything is in registers to pass to the call, emit the
- // call itself.
- if (InFlag.Val)
- CallOperands.push_back(InFlag); // Strong dep on register copies.
- else
- CallOperands.push_back(Chain); // Weak dep on whatever occurs before
- Chain = CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag,
- CallOperands);
-
- std::vector<SDOperand> CallResults;
-
- // If the call has results, copy the values out of the ret val registers.
- switch (N->getValueType(0)) {
- default: assert(0 && "Unexpected ret value!");
- case MVT::Other: break;
- case MVT::i32:
- if (N->getValueType(1) == MVT::i32) {
- Chain = CurDAG->getCopyFromReg(Chain, PPC::R4, MVT::i32,
- Chain.getValue(1)).getValue(1);
- CallResults.push_back(Chain.getValue(0));
- Chain = CurDAG->getCopyFromReg(Chain, PPC::R3, MVT::i32,
- Chain.getValue(1)).getValue(1);
- CallResults.push_back(Chain.getValue(0));
- } else {
- Chain = CurDAG->getCopyFromReg(Chain, PPC::R3, MVT::i32,
- Chain.getValue(1)).getValue(1);
- CallResults.push_back(Chain.getValue(0));
- }
- break;
- case MVT::f32:
- case MVT::f64:
- Chain = CurDAG->getCopyFromReg(Chain, PPC::F1, N->getValueType(0),
- Chain.getValue(1)).getValue(1);
- CallResults.push_back(Chain.getValue(0));
- break;
- }
-
- CallResults.push_back(Chain);
- CurDAG->ReplaceAllUsesWith(N, CallResults);
- return CallResults[Op.ResNo];
- }
case ISD::RET: {
SDOperand Chain = Select(N->getOperand(0)); // Token chain.
cast<BasicBlockSDNode>(N->getOperand(4))->getBasicBlock();
ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
SDOperand CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC);
- unsigned Opc = getBCCForSetCC(CC);
// If this is a two way branch, then grab the fallthrough basic block
// argument and build a PowerPC branch pseudo-op, suitable for long branch
// conversion if necessary by the branch selection pass. Otherwise, emit a
// standard conditional branch.
if (N->getOpcode() == ISD::BRTWOWAY_CC) {
- MachineBasicBlock *Fallthrough =
- cast<BasicBlockSDNode>(N->getOperand(5))->getBasicBlock();
+ SDOperand CondTrueBlock = N->getOperand(4);
+ SDOperand CondFalseBlock = N->getOperand(5);
+
+ // If the false case is the current basic block, then this is a self loop.
+ // We do not want to emit "Loop: ... brcond Out; br Loop", as it adds an
+ // extra dispatch group to the loop. Instead, invert the condition and
+ // emit "Loop: ... br!cond Loop; br Out
+ if (cast<BasicBlockSDNode>(CondFalseBlock)->getBasicBlock() == BB) {
+ std::swap(CondTrueBlock, CondFalseBlock);
+ CC = getSetCCInverse(CC,
+ MVT::isInteger(N->getOperand(2).getValueType()));
+ }
+
+ unsigned Opc = getBCCForSetCC(CC);
SDOperand CB = CurDAG->getTargetNode(PPC::COND_BRANCH, MVT::Other,
CondCode, getI32Imm(Opc),
- N->getOperand(4), N->getOperand(5),
+ CondTrueBlock, CondFalseBlock,
Chain);
- CurDAG->SelectNodeTo(N, PPC::B, MVT::Other, N->getOperand(5), CB);
+ CurDAG->SelectNodeTo(N, PPC::B, MVT::Other, CondFalseBlock, CB);
} else {
// Iterate to the next basic block
ilist<MachineBasicBlock>::iterator It = BB;
// the PowerPC Branch Selection pass to crash.
if (It == BB->getParent()->end()) It = Dest;
CurDAG->SelectNodeTo(N, PPC::COND_BRANCH, MVT::Other, CondCode,
- getI32Imm(Opc), N->getOperand(4),
+ getI32Imm(getBCCForSetCC(CC)), N->getOperand(4),
CurDAG->getBasicBlock(It), Chain);
}
return SDOperand(N, 0);
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