//
//===----------------------------------------------------------------------===//
+#define DEBUG_TYPE "ppc-codegen"
#include "PPC.h"
+#include "PPCPredicates.h"
#include "PPCTargetMachine.h"
#include "PPCISelLowering.h"
#include "PPCHazardRecognizers.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/Target/TargetOptions.h"
-#include "llvm/ADT/Statistic.h"
#include "llvm/Constants.h"
#include "llvm/GlobalValue.h"
#include "llvm/Intrinsics.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/Compiler.h"
-#include <iostream>
#include <queue>
#include <set>
using namespace llvm;
namespace {
- Statistic<> FrameOff("ppc-codegen", "Number of frame idx offsets collapsed");
-
//===--------------------------------------------------------------------===//
/// PPCDAGToDAGISel - PPC specific code to select PPC machine
/// instructions for SelectionDAG operations.
SDOperand &Base) {
return PPCLowering.SelectAddressRegImm(N, Disp, Base, *CurDAG);
}
+
+ /// SelectAddrImmOffs - Return true if the operand is valid for a preinc
+ /// immediate field. Because preinc imms have already been validated, just
+ /// accept it.
+ bool SelectAddrImmOffs(SDOperand Op, SDOperand N, SDOperand &Out) const {
+ Out = N;
+ return true;
+ }
/// SelectAddrIdx - Given the specified addressed, check to see if it can be
/// represented as an indexed [r+r] operation. Returns false if it can
private:
SDNode *SelectSETCC(SDOperand Op);
- SDNode *MySelect_PPCbctrl(SDOperand N);
- SDNode *MySelect_PPCcall(SDOperand N);
};
}
unsigned InVRSAVE = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
unsigned UpdatedVRSAVE = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
+ const TargetInstrInfo &TII = *TM.getInstrInfo();
MachineBasicBlock &EntryBB = *Fn.begin();
// Emit the following code into the entry block:
// InVRSAVE = MFVRSAVE
// UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE
// MTVRSAVE UpdatedVRSAVE
MachineBasicBlock::iterator IP = EntryBB.begin(); // Insert Point
- BuildMI(EntryBB, IP, PPC::MFVRSAVE, 0, InVRSAVE);
- BuildMI(EntryBB, IP, PPC::UPDATE_VRSAVE, 1, UpdatedVRSAVE).addReg(InVRSAVE);
- BuildMI(EntryBB, IP, PPC::MTVRSAVE, 1).addReg(UpdatedVRSAVE);
+ BuildMI(EntryBB, IP, TII.get(PPC::MFVRSAVE), InVRSAVE);
+ BuildMI(EntryBB, IP, TII.get(PPC::UPDATE_VRSAVE), UpdatedVRSAVE).addReg(InVRSAVE);
+ BuildMI(EntryBB, IP, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE);
// Find all return blocks, outputting a restore in each epilog.
- const TargetInstrInfo &TII = *TM.getInstrInfo();
for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
if (!BB->empty() && TII.isReturn(BB->back().getOpcode())) {
IP = BB->end(); --IP;
IP = I2;
// Emit: MTVRSAVE InVRSave
- BuildMI(*BB, IP, PPC::MTVRSAVE, 1).addReg(InVRSAVE);
+ BuildMI(*BB, IP, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE);
}
}
}
///
SDNode *PPCDAGToDAGISel::getGlobalBaseReg() {
if (!GlobalBaseReg) {
+ const TargetInstrInfo &TII = *TM.getInstrInfo();
// Insert the set of GlobalBaseReg into the first MBB of the function
MachineBasicBlock &FirstMBB = BB->getParent()->front();
MachineBasicBlock::iterator MBBI = FirstMBB.begin();
SSARegMap *RegMap = BB->getParent()->getSSARegMap();
- if (PPCLowering.getPointerTy() == MVT::i32)
+ if (PPCLowering.getPointerTy() == MVT::i32) {
GlobalBaseReg = RegMap->createVirtualRegister(PPC::GPRCRegisterClass);
- else
+ BuildMI(FirstMBB, MBBI, TII.get(PPC::MovePCtoLR), PPC::LR);
+ BuildMI(FirstMBB, MBBI, TII.get(PPC::MFLR), GlobalBaseReg);
+ } else {
GlobalBaseReg = RegMap->createVirtualRegister(PPC::G8RCRegisterClass);
-
- BuildMI(FirstMBB, MBBI, PPC::MovePCtoLR, 0, PPC::LR);
- BuildMI(FirstMBB, MBBI, PPC::MFLR, 1, GlobalBaseReg);
+ BuildMI(FirstMBB, MBBI, TII.get(PPC::MovePCtoLR8), PPC::LR8);
+ BuildMI(FirstMBB, MBBI, TII.get(PPC::MFLR8), GlobalBaseReg);
+ }
}
return CurDAG->getRegister(GlobalBaseReg, PPCLowering.getPointerTy()).Val;
}
return SDOperand(CurDAG->getTargetNode(Opc, MVT::i32, LHS, RHS), 0);
}
-/// getBCCForSetCC - Returns the PowerPC condition branch mnemonic corresponding
-/// to Condition.
-static unsigned getBCCForSetCC(ISD::CondCode CC) {
+static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) {
switch (CC) {
default: assert(0 && "Unknown condition!"); abort();
case ISD::SETOEQ: // FIXME: This is incorrect see PR642.
case ISD::SETUEQ:
- case ISD::SETEQ: return PPC::BEQ;
+ case ISD::SETEQ: return PPC::PRED_EQ;
case ISD::SETONE: // FIXME: This is incorrect see PR642.
case ISD::SETUNE:
- case ISD::SETNE: return PPC::BNE;
+ case ISD::SETNE: return PPC::PRED_NE;
case ISD::SETOLT: // FIXME: This is incorrect see PR642.
case ISD::SETULT:
- case ISD::SETLT: return PPC::BLT;
+ case ISD::SETLT: return PPC::PRED_LT;
case ISD::SETOLE: // FIXME: This is incorrect see PR642.
case ISD::SETULE:
- case ISD::SETLE: return PPC::BLE;
+ case ISD::SETLE: return PPC::PRED_LE;
case ISD::SETOGT: // FIXME: This is incorrect see PR642.
case ISD::SETUGT:
- case ISD::SETGT: return PPC::BGT;
+ case ISD::SETGT: return PPC::PRED_GT;
case ISD::SETOGE: // FIXME: This is incorrect see PR642.
case ISD::SETUGE:
- case ISD::SETGE: return PPC::BGE;
+ case ISD::SETGE: return PPC::PRED_GE;
- case ISD::SETO: return PPC::BNU;
- case ISD::SETUO: return PPC::BUN;
+ case ISD::SETO: return PPC::PRED_NU;
+ case ISD::SETUO: return PPC::PRED_UN;
}
- return 0;
}
/// getCRIdxForSetCC - Return the index of the condition register field
switch (N->getOpcode()) {
default: break;
+
+ case ISD::Constant: {
+ if (N->getValueType(0) == MVT::i64) {
+ // Get 64 bit value.
+ int64_t Imm = cast<ConstantSDNode>(N)->getValue();
+ // Assume no remaining bits.
+ unsigned Remainder = 0;
+ // Assume no shift required.
+ unsigned Shift = 0;
+
+ // If it can't be represented as a 32 bit value.
+ if (!isInt32(Imm)) {
+ Shift = CountTrailingZeros_64(Imm);
+ int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
+
+ // If the shifted value fits 32 bits.
+ if (isInt32(ImmSh)) {
+ // Go with the shifted value.
+ Imm = ImmSh;
+ } else {
+ // Still stuck with a 64 bit value.
+ Remainder = Imm;
+ Shift = 32;
+ Imm >>= 32;
+ }
+ }
+
+ // Intermediate operand.
+ SDNode *Result;
+
+ // Handle first 32 bits.
+ unsigned Lo = Imm & 0xFFFF;
+ unsigned Hi = (Imm >> 16) & 0xFFFF;
+
+ // Simple value.
+ if (isInt16(Imm)) {
+ // Just the Lo bits.
+ Result = CurDAG->getTargetNode(PPC::LI8, MVT::i64, getI32Imm(Lo));
+ } else if (Lo) {
+ // Handle the Hi bits.
+ unsigned OpC = Hi ? PPC::LIS8 : PPC::LI8;
+ Result = CurDAG->getTargetNode(OpC, MVT::i64, getI32Imm(Hi));
+ // And Lo bits.
+ Result = CurDAG->getTargetNode(PPC::ORI8, MVT::i64,
+ SDOperand(Result, 0), getI32Imm(Lo));
+ } else {
+ // Just the Hi bits.
+ Result = CurDAG->getTargetNode(PPC::LIS8, MVT::i64, getI32Imm(Hi));
+ }
+
+ // If no shift, we're done.
+ if (!Shift) return Result;
+
+ // Shift for next step if the upper 32-bits were not zero.
+ if (Imm) {
+ Result = CurDAG->getTargetNode(PPC::RLDICR, MVT::i64,
+ SDOperand(Result, 0),
+ getI32Imm(Shift), getI32Imm(63 - Shift));
+ }
+
+ // Add in the last bits as required.
+ if ((Hi = (Remainder >> 16) & 0xFFFF)) {
+ Result = CurDAG->getTargetNode(PPC::ORIS8, MVT::i64,
+ SDOperand(Result, 0), getI32Imm(Hi));
+ }
+ if ((Lo = Remainder & 0xFFFF)) {
+ Result = CurDAG->getTargetNode(PPC::ORI8, MVT::i64,
+ SDOperand(Result, 0), getI32Imm(Lo));
+ }
+
+ return Result;
+ }
+ break;
+ }
+
case ISD::SETCC:
return SelectSETCC(Op);
case PPCISD::GlobalBaseReg:
if (LD->getAddressingMode() != ISD::PRE_INC)
break;
- unsigned Opcode;
- bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
- if (LD->getValueType(0) != MVT::i64) {
- // Handle PPC32 integer and normal FP loads.
- assert(!isSExt || LoadedVT == MVT::i16 && "Invalid sext update load");
- switch (LoadedVT) {
- default: assert(0 && "Invalid PPC load type!");
- case MVT::f64: Opcode = PPC::LFDU; break;
- case MVT::f32: Opcode = PPC::LFSU; break;
- case MVT::i32: Opcode = PPC::LWZU; break;
- case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break;
- case MVT::i1:
- case MVT::i8: Opcode = PPC::LBZU; break;
- }
- } else {
- assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
- assert(!isSExt || LoadedVT == MVT::i16 && "Invalid sext update load");
- switch (LoadedVT) {
- default: assert(0 && "Invalid PPC load type!");
- case MVT::i64: Opcode = PPC::LDU; break;
- case MVT::i32: Opcode = PPC::LWZU8; break;
- case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break;
- case MVT::i1:
- case MVT::i8: Opcode = PPC::LBZU8; break;
- }
- }
-
SDOperand Offset = LD->getOffset();
- if (isa<ConstantSDNode>(Offset)) {
+ if (isa<ConstantSDNode>(Offset) ||
+ Offset.getOpcode() == ISD::TargetGlobalAddress) {
+
+ unsigned Opcode;
+ bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
+ if (LD->getValueType(0) != MVT::i64) {
+ // Handle PPC32 integer and normal FP loads.
+ assert(!isSExt || LoadedVT == MVT::i16 && "Invalid sext update load");
+ switch (LoadedVT) {
+ default: assert(0 && "Invalid PPC load type!");
+ case MVT::f64: Opcode = PPC::LFDU; break;
+ case MVT::f32: Opcode = PPC::LFSU; break;
+ case MVT::i32: Opcode = PPC::LWZU; break;
+ case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break;
+ case MVT::i1:
+ case MVT::i8: Opcode = PPC::LBZU; break;
+ }
+ } else {
+ assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
+ assert(!isSExt || LoadedVT == MVT::i16 && "Invalid sext update load");
+ switch (LoadedVT) {
+ default: assert(0 && "Invalid PPC load type!");
+ case MVT::i64: Opcode = PPC::LDU; break;
+ case MVT::i32: Opcode = PPC::LWZU8; break;
+ case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break;
+ case MVT::i1:
+ case MVT::i8: Opcode = PPC::LBZU8; break;
+ }
+ }
+
SDOperand Chain = LD->getChain();
SDOperand Base = LD->getBasePtr();
AddToISelQueue(Chain);
}
SDOperand CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC);
- unsigned BROpc = getBCCForSetCC(CC);
+ unsigned BROpc = getPredicateForSetCC(CC);
unsigned SelectCCOp;
if (N->getValueType(0) == MVT::i32)
getI32Imm(BROpc) };
return CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), Ops, 4);
}
+ case PPCISD::COND_BRANCH: {
+ AddToISelQueue(N->getOperand(0)); // Op #0 is the Chain.
+ // Op #1 is the PPC::PRED_* number.
+ // Op #2 is the CR#
+ // Op #3 is the Dest MBB
+ AddToISelQueue(N->getOperand(4)); // Op #4 is the Flag.
+ SDOperand Ops[] = { N->getOperand(1), N->getOperand(2), N->getOperand(3),
+ N->getOperand(0), N->getOperand(4) };
+ return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 5);
+ }
case ISD::BR_CC: {
AddToISelQueue(N->getOperand(0));
ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
SDOperand CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC);
- SDOperand Ops[] = { CondCode, getI32Imm(getBCCForSetCC(CC)),
+ SDOperand Ops[] = { getI32Imm(getPredicateForSetCC(CC)), CondCode,
N->getOperand(4), N->getOperand(0) };
- return CurDAG->SelectNodeTo(N, PPC::COND_BRANCH, MVT::Other, Ops, 4);
+ return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 4);
}
case ISD::BRIND: {
// FIXME: Should custom lower this.
Chain), 0);
return CurDAG->SelectNodeTo(N, PPC::BCTR, MVT::Other, Chain);
}
- // FIXME: These are manually selected because tblgen isn't handling varargs
- // nodes correctly.
- case PPCISD::BCTRL: return MySelect_PPCbctrl(Op);
- case PPCISD::CALL: return MySelect_PPCcall(Op);
}
return SelectCode(Op);
}
-// FIXME: This is manually selected because tblgen isn't handling varargs nodes
-// correctly.
-SDNode *PPCDAGToDAGISel::MySelect_PPCbctrl(SDOperand N) {
- SDOperand Chain(0, 0);
-
- bool hasFlag =
- N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag;
-
- SmallVector<SDOperand, 8> Ops;
- // Push varargs arguments, including optional flag.
- for (unsigned i = 1, e = N.getNumOperands()-hasFlag; i != e; ++i) {
- Chain = N.getOperand(i);
- AddToISelQueue(Chain);
- Ops.push_back(Chain);
- }
-
- Chain = N.getOperand(0);
- AddToISelQueue(Chain);
- Ops.push_back(Chain);
-
- if (hasFlag) {
- Chain = N.getOperand(N.getNumOperands()-1);
- AddToISelQueue(Chain);
- Ops.push_back(Chain);
- }
-
- return CurDAG->getTargetNode(PPC::BCTRL, MVT::Other, MVT::Flag,
- &Ops[0], Ops.size());
-}
-
-// FIXME: This is manually selected because tblgen isn't handling varargs nodes
-// correctly.
-SDNode *PPCDAGToDAGISel::MySelect_PPCcall(SDOperand N) {
- SDOperand Chain(0, 0);
- SDOperand N1(0, 0);
- SDOperand Tmp0(0, 0);
- Chain = N.getOperand(0);
- N1 = N.getOperand(1);
-
- // Pattern: (PPCcall:void (imm:i32):$func)
- // Emits: (BLA:void (imm:i32):$func)
- // Pattern complexity = 4 cost = 1
- if (N1.getOpcode() == ISD::Constant) {
- unsigned Tmp0C = (unsigned)cast<ConstantSDNode>(N1)->getValue();
-
- SmallVector<SDOperand, 8> Ops;
- Ops.push_back(CurDAG->getTargetConstant(Tmp0C, MVT::i32));
-
- bool hasFlag =
- N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag;
-
- // Push varargs arguments, not including optional flag.
- for (unsigned i = 2, e = N.getNumOperands()-hasFlag; i != e; ++i) {
- Chain = N.getOperand(i);
- AddToISelQueue(Chain);
- Ops.push_back(Chain);
- }
- Chain = N.getOperand(0);
- AddToISelQueue(Chain);
- Ops.push_back(Chain);
- if (hasFlag) {
- Chain = N.getOperand(N.getNumOperands()-1);
- AddToISelQueue(Chain);
- Ops.push_back(Chain);
- }
- return CurDAG->getTargetNode(PPC::BLA, MVT::Other, MVT::Flag,
- &Ops[0], Ops.size());
- }
-
- // Pattern: (PPCcall:void (tglobaladdr:i32):$dst)
- // Emits: (BL:void (tglobaladdr:i32):$dst)
- // Pattern complexity = 4 cost = 1
- if (N1.getOpcode() == ISD::TargetGlobalAddress) {
- SmallVector<SDOperand, 8> Ops;
- Ops.push_back(N1);
-
- bool hasFlag =
- N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag;
-
- // Push varargs arguments, not including optional flag.
- for (unsigned i = 2, e = N.getNumOperands()-hasFlag; i != e; ++i) {
- Chain = N.getOperand(i);
- AddToISelQueue(Chain);
- Ops.push_back(Chain);
- }
- Chain = N.getOperand(0);
- AddToISelQueue(Chain);
- Ops.push_back(Chain);
- if (hasFlag) {
- Chain = N.getOperand(N.getNumOperands()-1);
- AddToISelQueue(Chain);
- Ops.push_back(Chain);
- }
-
- return CurDAG->getTargetNode(PPC::BL, MVT::Other, MVT::Flag,
- &Ops[0], Ops.size());
- }
-
- // Pattern: (PPCcall:void (texternalsym:i32):$dst)
- // Emits: (BL:void (texternalsym:i32):$dst)
- // Pattern complexity = 4 cost = 1
- if (N1.getOpcode() == ISD::TargetExternalSymbol) {
- std::vector<SDOperand> Ops;
- Ops.push_back(N1);
-
- bool hasFlag =
- N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag;
-
- // Push varargs arguments, not including optional flag.
- for (unsigned i = 2, e = N.getNumOperands()-hasFlag; i != e; ++i) {
- Chain = N.getOperand(i);
- AddToISelQueue(Chain);
- Ops.push_back(Chain);
- }
- Chain = N.getOperand(0);
- AddToISelQueue(Chain);
- Ops.push_back(Chain);
- if (hasFlag) {
- Chain = N.getOperand(N.getNumOperands()-1);
- AddToISelQueue(Chain);
- Ops.push_back(Chain);
- }
-
- return CurDAG->getTargetNode(PPC::BL, MVT::Other, MVT::Flag,
- &Ops[0], Ops.size());
- }
- std::cerr << "Cannot yet select: ";
- N.Val->dump(CurDAG);
- std::cerr << '\n';
- abort();
-
- return NULL;
-}
-
/// createPPCISelDag - This pass converts a legalized DAG into a
/// PowerPC-specific DAG, ready for instruction scheduling.
projects / oota-llvm.git / blobdiff