[mips][sched] Split IIImul and IIImult into subclasses.

[oota-llvm.git] / lib / Target / Mips / MipsSchedule.td

diff --git a/lib/Target/Mips/MipsSchedule.td b/lib/Target/Mips/MipsSchedule.td
index 953fff0a5159b3da0f30cfca5a2e85de6ff15caa..904f89900c590c8d0343f6588f8a29f75efdb688 100644 (file)
--- a/lib/Target/Mips/MipsSchedule.td
+++ b/lib/Target/Mips/MipsSchedule.td
@@ -20,8 +20,6 @@ def IIAlu              : InstrItinClass;
 def IILoad             : InstrItinClass;
 def IIStore            : InstrItinClass;
 def IIBranch           : InstrItinClass;
-def IIImul             : InstrItinClass;
-def IIImult            : InstrItinClass;
 def IIIdiv             : InstrItinClass;
 def IIslt              : InstrItinClass;
 def IIFcvt             : InstrItinClass;
@@ -49,6 +47,8 @@ def II_CLO              : InstrItinClass;
 def II_CLZ              : InstrItinClass;
 def II_DADDIU           : InstrItinClass;
 def II_DADDU            : InstrItinClass;
+def II_DMULT            : InstrItinClass;
+def II_DMULTU           : InstrItinClass;
 def II_DROTR            : InstrItinClass;
 def II_DROTR32          : InstrItinClass;
 def II_DROTRV           : InstrItinClass;
@@ -63,12 +63,19 @@ def II_DSRL32           : InstrItinClass;
 def II_DSRLV            : InstrItinClass;
 def II_DSUBU            : InstrItinClass;
 def II_LUI              : InstrItinClass;
+def II_MADD             : InstrItinClass;
+def II_MADDU            : InstrItinClass;
 def II_MFHI_MFLO        : InstrItinClass; // mfhi and mflo
 def II_MTHI_MTLO        : InstrItinClass; // mthi and mtlo
 def II_MOVF             : InstrItinClass;
 def II_MOVN             : InstrItinClass;
 def II_MOVT             : InstrItinClass;
 def II_MOVZ             : InstrItinClass;
+def II_MUL              : InstrItinClass;
+def II_MULT             : InstrItinClass;
+def II_MULTU            : InstrItinClass;
+def II_MSUB             : InstrItinClass;
+def II_MSUBU            : InstrItinClass;
 def II_NOR              : InstrItinClass;
 def II_OR               : InstrItinClass;
 def II_ORI              : InstrItinClass;
@@ -133,10 +140,17 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
   InstrItinData<IILoad             , [InstrStage<3,  [ALU]>]>,
   InstrItinData<IIStore            , [InstrStage<1,  [ALU]>]>,
   InstrItinData<IIBranch           , [InstrStage<1,  [ALU]>]>,
+  InstrItinData<II_DMULT           , [InstrStage<17, [IMULDIV]>]>,
+  InstrItinData<II_DMULTU          , [InstrStage<17, [IMULDIV]>]>,
+  InstrItinData<II_MADD            , [InstrStage<17, [IMULDIV]>]>,
+  InstrItinData<II_MADDU           , [InstrStage<17, [IMULDIV]>]>,
   InstrItinData<II_MFHI_MFLO       , [InstrStage<1,  [IMULDIV]>]>,
+  InstrItinData<II_MSUB            , [InstrStage<17, [IMULDIV]>]>,
+  InstrItinData<II_MSUBU           , [InstrStage<17, [IMULDIV]>]>,
   InstrItinData<II_MTHI_MTLO       , [InstrStage<1,  [IMULDIV]>]>,
-  InstrItinData<IIImul             , [InstrStage<17, [IMULDIV]>]>,
-  InstrItinData<IIImult            , [InstrStage<17, [IMULDIV]>]>,
+  InstrItinData<II_MUL             , [InstrStage<17, [IMULDIV]>]>,
+  InstrItinData<II_MULT            , [InstrStage<17, [IMULDIV]>]>,
+  InstrItinData<II_MULTU           , [InstrStage<17, [IMULDIV]>]>,
   InstrItinData<IIIdiv             , [InstrStage<38, [IMULDIV]>]>,
   InstrItinData<IIFcvt             , [InstrStage<1,  [ALU]>]>,
   InstrItinData<IIFmove            , [InstrStage<2,  [ALU]>]>,