[Mips][msa] Added initial MSA support.

[oota-llvm.git] / lib / Target / Mips / MipsRegisterInfo.td

diff --git a/lib/Target/Mips/MipsRegisterInfo.td b/lib/Target/Mips/MipsRegisterInfo.td
index aa5d39c6a35c343150eebe853a2423a4ff3023ec..adc0a7972d7b53060e8a38c3b57507723e419e49 100644 (file)
--- a/lib/Target/Mips/MipsRegisterInfo.td
+++ b/lib/Target/Mips/MipsRegisterInfo.td
@@ -14,6 +14,7 @@ let Namespace = "Mips" in {
 def sub_fpeven : SubRegIndex<32>;
 def sub_fpodd  : SubRegIndex<32, 32>;
 def sub_32     : SubRegIndex<32>;
+def sub_64     : SubRegIndex<64>;
 def sub_lo     : SubRegIndex<32>;
 def sub_hi     : SubRegIndex<32, 32>;
 def sub_dsp16_19 : SubRegIndex<4, 16>;
@@ -63,6 +64,12 @@ class AFPR64<bits<16> Enc, string n, list<Register> subregs>
   let SubRegIndices = [sub_32];
 }
 
+// Mips 128-bit (aliased) MSA Registers
+class AFPR128<bits<16> Enc, string n, list<Register> subregs>
+  : MipsRegWithSubRegs<Enc, n, subregs> {
+  let SubRegIndices = [sub_64];
+}
+
 // Accumulator Registers
 class ACCReg<bits<16> Enc, string n, list<Register> subregs>
   : MipsRegWithSubRegs<Enc, n, subregs> {
@@ -162,6 +169,41 @@ let Namespace = "Mips" in {
   def D#I#_64 : AFPR64<I, "f"#I, [!cast<FPR>("F"#I)]>,
                 DwarfRegNum<[!add(I, 32)]>;
 
+  /// Mips MSA registers
+  /// MSA and FPU cannot both be present unless the FPU has 64-bit registers
+  def W0  : AFPR128<0, "w0", [D0_64]>, DwarfRegNum<[32]>;
+  def W1  : AFPR128<1, "w1", [D1_64]>, DwarfRegNum<[33]>;
+  def W2  : AFPR128<2, "w2", [D2_64]>, DwarfRegNum<[34]>;
+  def W3  : AFPR128<3, "w3", [D3_64]>, DwarfRegNum<[35]>;
+  def W4  : AFPR128<4, "w4", [D4_64]>, DwarfRegNum<[36]>;
+  def W5  : AFPR128<5, "w5", [D5_64]>, DwarfRegNum<[37]>;
+  def W6  : AFPR128<6, "w6", [D6_64]>, DwarfRegNum<[38]>;
+  def W7  : AFPR128<7, "w7", [D7_64]>, DwarfRegNum<[39]>;
+  def W8  : AFPR128<8, "w8", [D8_64]>, DwarfRegNum<[40]>;
+  def W9  : AFPR128<9, "w9", [D9_64]>, DwarfRegNum<[41]>;
+  def W10 : AFPR128<10, "w10", [D10_64]>, DwarfRegNum<[42]>;
+  def W11 : AFPR128<11, "w11", [D11_64]>, DwarfRegNum<[43]>;
+  def W12 : AFPR128<12, "w12", [D12_64]>, DwarfRegNum<[44]>;
+  def W13 : AFPR128<13, "w13", [D13_64]>, DwarfRegNum<[45]>;
+  def W14 : AFPR128<14, "w14", [D14_64]>, DwarfRegNum<[46]>;
+  def W15 : AFPR128<15, "w15", [D15_64]>, DwarfRegNum<[47]>;
+  def W16 : AFPR128<16, "w16", [D16_64]>, DwarfRegNum<[48]>;
+  def W17 : AFPR128<17, "w17", [D17_64]>, DwarfRegNum<[49]>;
+  def W18 : AFPR128<18, "w18", [D18_64]>, DwarfRegNum<[50]>;
+  def W19 : AFPR128<19, "w19", [D19_64]>, DwarfRegNum<[51]>;
+  def W20 : AFPR128<20, "w20", [D20_64]>, DwarfRegNum<[52]>;
+  def W21 : AFPR128<21, "w21", [D21_64]>, DwarfRegNum<[53]>;
+  def W22 : AFPR128<22, "w22", [D22_64]>, DwarfRegNum<[54]>;
+  def W23 : AFPR128<23, "w23", [D23_64]>, DwarfRegNum<[55]>;
+  def W24 : AFPR128<24, "w24", [D24_64]>, DwarfRegNum<[56]>;
+  def W25 : AFPR128<25, "w25", [D25_64]>, DwarfRegNum<[57]>;
+  def W26 : AFPR128<26, "w26", [D26_64]>, DwarfRegNum<[58]>;
+  def W27 : AFPR128<27, "w27", [D27_64]>, DwarfRegNum<[59]>;
+  def W28 : AFPR128<28, "w28", [D28_64]>, DwarfRegNum<[60]>;
+  def W29 : AFPR128<29, "w29", [D29_64]>, DwarfRegNum<[61]>;
+  def W30 : AFPR128<30, "w30", [D30_64]>, DwarfRegNum<[62]>;
+  def W31 : AFPR128<31, "w31", [D31_64]>, DwarfRegNum<[63]>;
+
   // Hi/Lo registers
   def HI  : Register<"ac0">, DwarfRegNum<[64]>;
   def HI1 : Register<"ac1">, DwarfRegNum<[176]>;
@@ -302,6 +344,9 @@ def CCR : RegisterClass<"Mips", [i32], 32, (sequence "FCR%u", 0, 31)>,
 def FCC : RegisterClass<"Mips", [i32], 32, (sequence "FCC%u", 0, 7)>,
           Unallocatable;
 
+def MSA128: RegisterClass<"Mips", [v16i8, v8i16, v4i32, v2i64], 128,
+                          (sequence "W%u", 0, 31)>;
+
 // Hi/Lo Registers
 def LORegs : RegisterClass<"Mips", [i32], 32, (add LO)>;
 def HIRegs : RegisterClass<"Mips", [i32], 32, (add HI)>;