Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism."

[oota-llvm.git] / lib / Target / Mips / MipsRegisterInfo.td

diff --git a/lib/Target/Mips/MipsRegisterInfo.td b/lib/Target/Mips/MipsRegisterInfo.td
index be78a2266268c61d24002fec53e3ab36bc60ad08..576110d77cc3ad187b258d6308e548a4a8e0f9a8 100644 (file)
--- a/lib/Target/Mips/MipsRegisterInfo.td
+++ b/lib/Target/Mips/MipsRegisterInfo.td
@@ -34,14 +34,9 @@ class FPR<bits<5> num, string n> : MipsReg<n> {
 }
 
 // Mips 64-bit (aliased) FPU Registers
-let Namespace = "Mips" in {
-def sub_fpeven : SubRegIndex;
-def sub_fpodd  : SubRegIndex;
-}
-class AFPR<bits<5> num, string n, list<Register> subregs>
+class AFPR<bits<5> num, string n, list<Register> subregs> 
   : MipsRegWithSubRegs<n, subregs> {
   let Num = num;
-  let SubRegIndices = [sub_fpeven, sub_fpodd];
 }
 
 //===----------------------------------------------------------------------===//
@@ -145,6 +140,25 @@ let Namespace = "Mips" in {
   def FCR31 : Register<"31">;
 }
 
+//===----------------------------------------------------------------------===//
+// Subregister Set Definitions
+//===----------------------------------------------------------------------===//
+
+let Namespace = "Mips" in {
+def sub_fpeven : SubRegIndex;
+def sub_fpodd  : SubRegIndex;
+}
+
+def : SubRegSet<sub_fpeven, [D0, D1, D2, D3, D4, D5, D6, D7,
+                             D8, D9, D10, D11, D12, D13, D14, D15],
+                            [F0, F2, F4, F6, F8, F10, F12, F14,
+                             F16, F18, F20, F22, F24, F26, F28, F30]>;
+
+def : SubRegSet<sub_fpodd, [D0, D1, D2, D3, D4, D5, D6, D7,
+                            D8, D9, D10, D11, D12, D13, D14, D15],
+                           [F1, F3, F5, F7, F9, F11, F13, F15,
+                            F17, F19, F21, F23, F25, F27, F29, F31]>;
+
 //===----------------------------------------------------------------------===//
 // Register Classes
 //===----------------------------------------------------------------------===//