//
// The LLVM Compiler Infrastructure
//
-// This file was developed by Bruno Cardoso Lopes and is distributed under the
-// University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
-// This file contains the MIPS implementation of the MRegisterInfo class.
+// This file contains the MIPS implementation of the TargetRegisterInfo class.
//
//===----------------------------------------------------------------------===//
#include "llvm/Support/Debug.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/STLExtras.h"
-//#include "MipsSubtarget.h"
using namespace llvm;
-// TODO: add subtarget support
MipsRegisterInfo::MipsRegisterInfo(const TargetInstrInfo &tii)
: MipsGenRegisterInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
- TII(tii) {}
+ TII(tii) {}
/// getRegisterNumbering - Given the enum value for some register, e.g.
/// Mips::RA, return the number that it corresponds to (e.g. 31).
getRegisterNumbering(unsigned RegEnum)
{
switch (RegEnum) {
- case Mips::ZERO : return 0;
- case Mips::AT : return 1;
- case Mips::V0 : return 2;
- case Mips::V1 : return 3;
- case Mips::A0 : return 4;
- case Mips::A1 : return 5;
- case Mips::A2 : return 6;
- case Mips::A3 : return 7;
- case Mips::T0 : return 8;
- case Mips::T1 : return 9;
- case Mips::T2 : return 10;
- case Mips::T3 : return 11;
- case Mips::T4 : return 12;
- case Mips::T5 : return 13;
- case Mips::T6 : return 14;
- case Mips::T7 : return 15;
- case Mips::T8 : return 16;
- case Mips::T9 : return 17;
- case Mips::S0 : return 18;
- case Mips::S1 : return 19;
- case Mips::S2 : return 20;
- case Mips::S3 : return 21;
- case Mips::S4 : return 22;
- case Mips::S5 : return 23;
- case Mips::S6 : return 24;
- case Mips::S7 : return 25;
- case Mips::K0 : return 26;
- case Mips::K1 : return 27;
- case Mips::GP : return 28;
- case Mips::SP : return 29;
- case Mips::FP : return 30;
- case Mips::RA : return 31;
+ case Mips::ZERO : case Mips::F0 : return 0;
+ case Mips::AT : case Mips::F1 : return 1;
+ case Mips::V0 : case Mips::F2 : return 2;
+ case Mips::V1 : case Mips::F3 : return 3;
+ case Mips::A0 : case Mips::F4 : return 4;
+ case Mips::A1 : case Mips::F5 : return 5;
+ case Mips::A2 : case Mips::F6 : return 6;
+ case Mips::A3 : case Mips::F7 : return 7;
+ case Mips::T0 : case Mips::F8 : return 8;
+ case Mips::T1 : case Mips::F9 : return 9;
+ case Mips::T2 : case Mips::F10: return 10;
+ case Mips::T3 : case Mips::F11: return 11;
+ case Mips::T4 : case Mips::F12: return 12;
+ case Mips::T5 : case Mips::F13: return 13;
+ case Mips::T6 : case Mips::F14: return 14;
+ case Mips::T7 : case Mips::F15: return 15;
+ case Mips::T8 : case Mips::F16: return 16;
+ case Mips::T9 : case Mips::F17: return 17;
+ case Mips::S0 : case Mips::F18: return 18;
+ case Mips::S1 : case Mips::F19: return 19;
+ case Mips::S2 : case Mips::F20: return 20;
+ case Mips::S3 : case Mips::F21: return 21;
+ case Mips::S4 : case Mips::F22: return 22;
+ case Mips::S5 : case Mips::F23: return 23;
+ case Mips::S6 : case Mips::F24: return 24;
+ case Mips::S7 : case Mips::F25: return 25;
+ case Mips::K0 : case Mips::F26: return 26;
+ case Mips::K1 : case Mips::F27: return 27;
+ case Mips::GP : case Mips::F28: return 28;
+ case Mips::SP : case Mips::F29: return 29;
+ case Mips::FP : case Mips::F30: return 30;
+ case Mips::RA : case Mips::F31: return 31;
default: assert(0 && "Unknown register number!");
}
-}
-
-void MipsRegisterInfo::
-storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
- unsigned SrcReg, int FI,
- const TargetRegisterClass *RC) const
-{
- if (RC == Mips::CPURegsRegisterClass)
- BuildMI(MBB, I, TII.get(Mips::SW)).addReg(SrcReg, false, false, true)
- .addImm(0).addFrameIndex(FI);
- else
- assert(0 && "Can't store this register to stack slot");
-}
-
-void MipsRegisterInfo::
-loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
- unsigned DestReg, int FI,
- const TargetRegisterClass *RC) const
-{
- if (RC == Mips::CPURegsRegisterClass)
- BuildMI(MBB, I, TII.get(Mips::LW), DestReg).addImm(0).addFrameIndex(FI);
- else
- assert(0 && "Can't load this register from stack slot");
-}
-
-void MipsRegisterInfo::
-copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
- unsigned DestReg, unsigned SrcReg,
- const TargetRegisterClass *RC) const
-{
- if (RC == Mips::CPURegsRegisterClass)
- BuildMI(MBB, I, TII.get(Mips::ADDu), DestReg).addReg(Mips::ZERO)
- .addReg(SrcReg);
- else
- assert (0 && "Can't copy this register");
-}
-
-void MipsRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator I,
- unsigned DestReg,
- const MachineInstr *Orig) const
-{
- MachineInstr *MI = Orig->clone();
- MI->getOperand(0).setReg(DestReg);
- MBB.insert(I, MI);
-}
-
-MachineInstr *MipsRegisterInfo::
-foldMemoryOperand(MachineInstr* MI, unsigned OpNum, int FI) const
-{
- MachineInstr *NewMI = NULL;
-
- switch (MI->getOpcode())
- {
- case Mips::ADDu:
- if ((MI->getOperand(0).isRegister()) &&
- (MI->getOperand(1).isRegister()) &&
- (MI->getOperand(1).getReg() == Mips::ZERO) &&
- (MI->getOperand(2).isRegister()))
- {
- if (OpNum == 0) // COPY -> STORE
- NewMI = BuildMI(TII.get(Mips::SW)).addFrameIndex(FI)
- .addImm(0).addReg(MI->getOperand(2).getReg());
- else // COPY -> LOAD
- NewMI = BuildMI(TII.get(Mips::LW), MI->getOperand(0)
- .getReg()).addImm(0).addFrameIndex(FI);
- }
- break;
- }
-
- if (NewMI)
- NewMI->copyKillDeadInfo(MI);
- return NewMI;
+ return 0; // Not reached
}
//===----------------------------------------------------------------------===//
const unsigned* MipsRegisterInfo::
getCalleeSavedRegs(const MachineFunction *MF) const
{
- // Mips calle-save register range is $16-$26(s0-s7)
+ // Mips callee-save register range is $16-$23(s0-s7)
static const unsigned CalleeSavedRegs[] = {
Mips::S0, Mips::S1, Mips::S2, Mips::S3,
Mips::S4, Mips::S5, Mips::S6, Mips::S7, 0
};
+
return CalleeSavedRegs;
}
//
// 0 ----------
// 4 Args to pass
-// . saved $GP (used in PIC - not supported yet)
+// . saved $GP (used in PIC)
// . Local Area
// . saved "Callee Saved" Registers
// . saved FP
eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
RegScavenger *RS) const
{
- MachineInstr &MI = *II;
+ MachineInstr &MI = *II;
MachineFunction &MF = *MI.getParent()->getParent();
unsigned i = 0;
"Instr doesn't have FrameIndex operand!");
}
- int FrameIndex = MI.getOperand(i).getFrameIndex();
+ int FrameIndex = MI.getOperand(i).getIndex();
int stackSize = MF.getFrameInfo()->getStackSize();
int spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
#endif
MI.getOperand(i-1).ChangeToImmediate(Offset);
- MI.getOperand(i).ChangeToRegister(getFrameRegister(MF),false);
+ MI.getOperand(i).ChangeToRegister(getFrameRegister(MF), false);
}
void MipsRegisterInfo::
MachineFrameInfo *MFI = MF.getFrameInfo();
MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
MachineBasicBlock::iterator MBBI = MBB.begin();
+ bool isPIC = (MF.getTarget().getRelocationModel() == Reloc::PIC_);
- // Replace the dummy '0' SPOffset by the negative offsets, as
- // explained on LowerFORMAL_ARGUMENTS
+ // Replace the dummy '0' SPOffset by the negative
+ // offsets, as explained on LowerFORMAL_ARGUMENTS
MipsFI->adjustLoadArgsFI(MFI);
MipsFI->adjustStoreVarArgsFI(MFI);
int FPOffset, RAOffset;
// Allocate space for saved RA and FP when needed
+ // FIXME: within 64-bit registers, change hardcoded
+ // sizes for RA and FP offsets.
if ((hasFP(MF)) && (MFI->hasCalls())) {
FPOffset = NumBytes;
RAOffset = (NumBytes+4);
FPOffset = NumBytes;
RAOffset = 0;
NumBytes += 4;
+ } else { // No calls and no fp.
+ RAOffset = FPOffset = 0;
}
MFI->setObjectOffset(MFI->CreateStackObject(4,4), FPOffset);
// Update frame info
MFI->setStackSize(NumBytes);
+ // PIC speficic function prologue
+ if (isPIC)
+ BuildMI(MBB, MBBI, TII.get(Mips::CPLOAD)).addReg(Mips::T9);
+
// Adjust stack : addi sp, sp, (-imm)
BuildMI(MBB, MBBI, TII.get(Mips::ADDiu), Mips::SP)
.addReg(Mips::SP).addImm(-NumBytes);
BuildMI(MBB, MBBI, TII.get(Mips::ADDu), Mips::FP)
.addReg(Mips::SP).addReg(Mips::ZERO);
}
+
+ // PIC speficic function prologue
+ if ((isPIC) && (MFI->hasCalls()))
+ BuildMI(MBB, MBBI, TII.get(Mips::CPRESTORE))
+ .addImm(MipsFI->getGPStackOffset());
}
void MipsRegisterInfo::
// lw $ra, stack_loc($sp)
if (MFI->hasCalls()) {
BuildMI(MBB, MBBI, TII.get(Mips::LW))
- .addReg(Mips::RA).addImm(RAOffset).addReg(Mips::SP);
+ .addReg(Mips::RA).addImm(RAOffset).addReg(Mips::SP);
}
// adjust stack : insert addi sp, sp, (imm)
void MipsRegisterInfo::
processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
+ // Set the SPOffset on the FI where GP must be saved/loaded.
+ MachineFrameInfo *MFI = MF.getFrameInfo();
+ if (MFI->hasCalls()) {
+ MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
+ #ifndef NDEBUG
+ DOUT << "processFunctionBeforeFrameFinalized\n";
+ DOUT << "GPOffset :" << MipsFI->getGPStackOffset() << "\n";
+ DOUT << "FI :" << MipsFI->getGPFI() << "\n";
+ #endif
+ MFI->setObjectOffset(MipsFI->getGPFI(), MipsFI->getGPStackOffset());
+ }
}
unsigned MipsRegisterInfo::
return 0;
}
+int MipsRegisterInfo::
+getDwarfRegNum(unsigned RegNum, bool isEH) const {
+ assert(0 && "What is the dwarf register number");
+ return -1;
+}
+
#include "MipsGenRegisterInfo.inc"
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