[mips] Marked up instructions added in MIPS-IV and tested that IAS for -mcpu=mips...

[oota-llvm.git] / lib / Target / Mips / MipsInstrInfo.td

diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td
index 687345830fab06d071816047191679cef96ec9b6..540cd230ea51caa0ad519d706d08a5801e881f52 100644 (file)
--- a/lib/Target/Mips/MipsInstrInfo.td
+++ b/lib/Target/Mips/MipsInstrInfo.td
@@ -160,6 +160,8 @@ def HasMips3_32  :    Predicate<"Subtarget.hasMips3_32()">,
                       AssemblerPredicate<"FeatureMips3_32">;
 def HasMips3     :    Predicate<"Subtarget.hasMips3()">,
                       AssemblerPredicate<"FeatureMips3">;
+def HasMips4_32  :    Predicate<"Subtarget.hasMips4_32()">,
+                      AssemblerPredicate<"FeatureMips4_32">;
 def HasMips32    :    Predicate<"Subtarget.hasMips32()">,
                       AssemblerPredicate<"FeatureMips32">;
 def HasMips32r2  :    Predicate<"Subtarget.hasMips32r2()">,
@@ -218,6 +220,9 @@ class ISA_MIPS64R2 { list<Predicate> InsnPredicates = [HasMips64r2]; }
 // The portions of MIPS-III that were also added to MIPS32
 class INSN_MIPS3_32 { list<Predicate> InsnPredicates = [HasMips3_32]; }
 
+// The portions of MIPS-IV that were also added to MIPS32
+class INSN_MIPS4_32 { list<Predicate> InsnPredicates = [HasMips4_32]; }
+
 class INSN_SWAP { list<Predicate> InsnPredicates = [HasSwap]; }
 class INSN_SEINREG { list<Predicate> InsnPredicates = [HasSEInReg]; }