let ValueCols = [["se"], ["micromips"]];
}
+class StdMMR6Rel;
+
+def Std2MicroMipsR6 : InstrMapping {
+ let FilterClass = "StdMMR6Rel";
+ // Instructions with the same BaseOpcode and isNVStore values form a row.
+ let RowFields = ["BaseOpcode"];
+ // Instructions with the same predicate sense form a column.
+ let ColFields = ["Arch"];
+ // The key column is the unpredicated instructions.
+ let KeyCol = ["se"];
+ // Value columns are PredSense=true and PredSense=false
+ let ValueCols = [["se"], ["micromipsr6"]];
+}
+
class StdArch {
string Arch = "se";
}
let Inst{15-0} = offset;
}
+class BBIT_FM<bits<6> op> : StdArch {
+ bits<5> rs;
+ bits<5> p;
+ bits<16> offset;
+
+ bits<32> Inst;
+
+ let Inst{31-26} = op;
+ let Inst{25-21} = rs;
+ let Inst{20-16} = p;
+ let Inst{15-0} = offset;
+}
+
class SLTI_FM<bits<6> op> : StdArch {
bits<5> rt;
bits<5> rs;
let Inst{5-0} = 0xf;
}
+class SYNCI_FM : StdArch {
+ // Produced by the mem_simm16 address as reg << 16 | imm (see getMemEncoding).
+ bits<21> addr;
+ bits<5> rs = addr{20-16};
+ bits<16> offset = addr{15-0};
+
+ bits<32> Inst;
+
+ let Inst{31-26} = 0b000001;
+ let Inst{25-21} = rs;
+ let Inst{20-16} = 0b11111;
+ let Inst{15-0} = offset;
+}
+
class MULT_FM<bits<6> op, bits<6> funct> : StdArch {
bits<5> rs;
bits<5> rt;
let Inst{5-0} = funct;
}
-class RDHWR_FM {
+class RDHWR_FM : StdArch {
bits<5> rt;
bits<5> rd;
bits<5> fs;
bits<5> ft;
bits<4> cond;
- bits<3> cc;
bits<32> Inst;
let Inst{25-21} = fmt;
let Inst{20-16} = ft;
let Inst{15-11} = fs;
- let Inst{10-8} = cc;
+ let Inst{10-8} = 0; // cc
let Inst{7-4} = 0x3;
let Inst{3-0} = cond;
}