//
// The LLVM Compiler Infrastructure
//
-// This file was developed by Bruno Cardoso Lopes is distributed under the
-// University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
//===----------------------------------------------------------------------===//
#define DEBUG_TYPE "mips-isel"
-
#include "Mips.h"
#include "MipsISelLowering.h"
+#include "MipsMachineFunction.h"
#include "MipsRegisterInfo.h"
#include "MipsSubtarget.h"
#include "MipsTargetMachine.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Support/Compiler.h"
/// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
/// make the right decision when generating code for different targets.
- //TODO: add initialization on constructor
- //const MipsSubtarget *Subtarget;
+ const MipsSubtarget &Subtarget;
public:
- MipsDAGToDAGISel(MipsTargetMachine &tm) :
- SelectionDAGISel(MipsLowering),
- TM(tm), MipsLowering(*TM.getTargetLowering()) {}
+ MipsDAGToDAGISel(MipsTargetMachine &tm) : SelectionDAGISel(MipsLowering),
+ TM(tm), MipsLowering(*TM.getTargetLowering()),
+ Subtarget(tm.getSubtarget<MipsSubtarget>()) {}
- virtual void InstructionSelectBasicBlock(SelectionDAG &SD);
+ virtual void InstructionSelect(SelectionDAG &SD);
// Pass Name
virtual const char *getPassName() const {
// Include the pieces autogenerated from the target description.
#include "MipsGenDAGISel.inc"
+ SDOperand getGlobalBaseReg();
SDNode *Select(SDOperand N);
// Complex Pattern.
}
-/// InstructionSelectBasicBlock - This callback is invoked by
+/// InstructionSelect - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
void MipsDAGToDAGISel::
-InstructionSelectBasicBlock(SelectionDAG &SD)
+InstructionSelect(SelectionDAG &SD)
{
DEBUG(BB->dump());
// Codegen the basic block.
#endif
SD.RemoveDeadNodes();
-
- // Emit machine code to BB.
- ScheduleAndEmitDAG(SD);
+}
+
+/// getGlobalBaseReg - Output the instructions required to put the
+/// GOT address into a register.
+SDOperand MipsDAGToDAGISel::getGlobalBaseReg() {
+ MachineFunction* MF = BB->getParent();
+ unsigned GP = 0;
+ for(MachineRegisterInfo::livein_iterator ii = MF->getRegInfo().livein_begin(),
+ ee = MF->getRegInfo().livein_end(); ii != ee; ++ii)
+ if (ii->first == Mips::GP) {
+ GP = ii->second;
+ break;
+ }
+ assert(GP && "GOT PTR not in liveins");
+ return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
+ GP, MVT::i32);
}
/// ComplexPattern used on MipsInstrInfo
return true;
}
- // TargetExternalSymbol and TargetGlobalAddress are
- // lowered and their addresses go into registers, so
- // they should not be touched here.
- if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
- Addr.getOpcode() == ISD::TargetGlobalAddress))
- return false;
+ // on PIC code Load GA
+ if (TM.getRelocationModel() == Reloc::PIC_) {
+ if ((Addr.getOpcode() == ISD::TargetGlobalAddress) ||
+ (Addr.getOpcode() == ISD::TargetJumpTable)){
+ Base = CurDAG->getRegister(Mips::GP, MVT::i32);
+ Offset = Addr;
+ return true;
+ }
+ } else {
+ if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
+ Addr.getOpcode() == ISD::TargetGlobalAddress))
+ return false;
+ }
// Operand is a result from an ADD.
- if (Addr.getOpcode() == ISD::ADD)
- {
- if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
- {
- if (Predicate_immSExt16(CN))
- {
+ if (Addr.getOpcode() == ISD::ADD) {
+ if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
+ if (Predicate_immSExt16(CN)) {
+
// If the first operand is a FI, get the TargetFI Node
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
(Addr.getOperand(0))) {
default: break;
- /// Special Mul operations
+ case ISD::SUBE:
+ case ISD::ADDE: {
+ SDOperand InFlag = Node->getOperand(2), CmpLHS;
+ unsigned Opc = InFlag.getOpcode(), MOp;
+
+ assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
+ (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
+ "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
+
+ if (Opcode == ISD::ADDE) {
+ CmpLHS = InFlag.getValue(0);
+ MOp = Mips::ADDu;
+ } else {
+ CmpLHS = InFlag.getOperand(0);
+ MOp = Mips::SUBu;
+ }
+
+ SDOperand Ops[] = { CmpLHS, InFlag.getOperand(1) };
+
+ SDOperand LHS = Node->getOperand(0);
+ SDOperand RHS = Node->getOperand(1);
+ AddToISelQueue(LHS);
+ AddToISelQueue(RHS);
+
+ MVT VT = LHS.getValueType();
+ SDNode *Carry = CurDAG->getTargetNode(Mips::SLTu, VT, Ops, 2);
+ SDNode *AddCarry = CurDAG->getTargetNode(Mips::ADDu, VT,
+ SDOperand(Carry,0), RHS);
+
+ return CurDAG->SelectNodeTo(N.Val, MOp, VT, MVT::Flag,
+ LHS, SDOperand(AddCarry,0));
+ }
+
+ /// Mul/Div with two results
+ case ISD::SDIVREM:
+ case ISD::UDIVREM:
+ case ISD::SMUL_LOHI:
+ case ISD::UMUL_LOHI: {
+ SDOperand Op1 = Node->getOperand(0);
+ SDOperand Op2 = Node->getOperand(1);
+ AddToISelQueue(Op1);
+ AddToISelQueue(Op2);
+
+ unsigned Op;
+ if (Opcode == ISD::UMUL_LOHI || Opcode == ISD::SMUL_LOHI)
+ Op = (Opcode == ISD::UMUL_LOHI ? Mips::MULTu : Mips::MULT);
+ else
+ Op = (Opcode == ISD::UDIVREM ? Mips::DIVu : Mips::DIV);
+
+ SDNode *Node = CurDAG->getTargetNode(Op, MVT::Flag, Op1, Op2);
+
+ SDOperand InFlag = SDOperand(Node, 0);
+ SDNode *Lo = CurDAG->getTargetNode(Mips::MFLO, MVT::i32, MVT::Flag, InFlag);
+
+ InFlag = SDOperand(Lo,1);
+ SDNode *Hi = CurDAG->getTargetNode(Mips::MFHI, MVT::i32, InFlag);
+
+ if (!N.getValue(0).use_empty())
+ ReplaceUses(N.getValue(0), SDOperand(Lo,0));
+
+ if (!N.getValue(1).use_empty())
+ ReplaceUses(N.getValue(1), SDOperand(Hi,0));
+
+ return NULL;
+ }
+
+ /// Special Muls
+ case ISD::MUL:
case ISD::MULHS:
case ISD::MULHU: {
SDOperand MulOp1 = Node->getOperand(0);
unsigned MulOp = (Opcode == ISD::MULHU ? Mips::MULTu : Mips::MULT);
SDNode *MulNode = CurDAG->getTargetNode(MulOp, MVT::Flag, MulOp1, MulOp2);
- SDOperand MFInFlag = SDOperand(MulNode, 0);
- return CurDAG->getTargetNode(Mips::MFHI, MVT::i32, MFInFlag);
+ SDOperand InFlag = SDOperand(MulNode, 0);
+
+ if (MulOp == ISD::MUL)
+ return CurDAG->getTargetNode(Mips::MFLO, MVT::i32, InFlag);
+ else
+ return CurDAG->getTargetNode(Mips::MFHI, MVT::i32, InFlag);
}
- /// Div operations
+ /// Div/Rem operations
+ case ISD::SREM:
+ case ISD::UREM:
case ISD::SDIV:
case ISD::UDIV: {
- SDOperand DivOp1 = Node->getOperand(0);
- SDOperand DivOp2 = Node->getOperand(1);
- AddToISelQueue(DivOp1);
- AddToISelQueue(DivOp2);
+ SDOperand Op1 = Node->getOperand(0);
+ SDOperand Op2 = Node->getOperand(1);
+ AddToISelQueue(Op1);
+ AddToISelQueue(Op2);
+
+ unsigned Op, MOp;
+ if (Opcode == ISD::SDIV || Opcode == ISD::UDIV) {
+ Op = (Opcode == ISD::SDIV ? Mips::DIV : Mips::DIVu);
+ MOp = Mips::MFLO;
+ } else {
+ Op = (Opcode == ISD::SREM ? Mips::DIV : Mips::DIVu);
+ MOp = Mips::MFHI;
+ }
+ SDNode *Node = CurDAG->getTargetNode(Op, MVT::Flag, Op1, Op2);
- unsigned DivOp = (Opcode == ISD::SDIV ? Mips::DIV : Mips::DIVu);
- SDNode *DivNode = CurDAG->getTargetNode(DivOp, MVT::Flag, DivOp1, DivOp2);
+ SDOperand InFlag = SDOperand(Node, 0);
+ return CurDAG->getTargetNode(MOp, MVT::i32, InFlag);
+ }
- SDOperand MFInFlag = SDOperand(DivNode, 0);
- return CurDAG->getTargetNode(Mips::MFLO, MVT::i32, MFInFlag);
+ // Get target GOT address.
+ case ISD::GLOBAL_OFFSET_TABLE: {
+ SDOperand Result = getGlobalBaseReg();
+ ReplaceUses(N, Result);
+ return NULL;
}
- /// Rem operations
- case ISD::SREM:
- case ISD::UREM: {
- SDOperand RemOp1 = Node->getOperand(0);
- SDOperand RemOp2 = Node->getOperand(1);
- AddToISelQueue(RemOp1);
- AddToISelQueue(RemOp2);
-
- unsigned RemOp = (Opcode == ISD::SREM ? Mips::DIV : Mips::DIVu);
- SDNode *RemNode = CurDAG->getTargetNode(RemOp, MVT::Flag, RemOp1, RemOp2);
-
- SDOperand MFInFlag = SDOperand(RemNode, 0);
- return CurDAG->getTargetNode(Mips::MFHI, MVT::i32, MFInFlag);
+ /// Handle direct and indirect calls when using PIC. On PIC, when
+ /// GOT is smaller than about 64k (small code) the GA target is
+ /// loaded with only one instruction. Otherwise GA's target must
+ /// be loaded with 3 instructions.
+ case MipsISD::JmpLink: {
+ if (TM.getRelocationModel() == Reloc::PIC_) {
+ //bool isCodeLarge = (TM.getCodeModel() == CodeModel::Large);
+ SDOperand Chain = Node->getOperand(0);
+ SDOperand Callee = Node->getOperand(1);
+ AddToISelQueue(Chain);
+ SDOperand T9Reg = CurDAG->getRegister(Mips::T9, MVT::i32);
+ SDOperand InFlag(0, 0);
+
+ if ( (isa<GlobalAddressSDNode>(Callee)) ||
+ (isa<ExternalSymbolSDNode>(Callee)) )
+ {
+ /// Direct call for global addresses and external symbols
+ SDOperand GPReg = CurDAG->getRegister(Mips::GP, MVT::i32);
+
+ // Use load to get GOT target
+ SDOperand Ops[] = { Callee, GPReg, Chain };
+ SDOperand Load = SDOperand(CurDAG->getTargetNode(Mips::LW, MVT::i32,
+ MVT::Other, Ops, 3), 0);
+ Chain = Load.getValue(1);
+ AddToISelQueue(Chain);
+
+ // Call target must be on T9
+ Chain = CurDAG->getCopyToReg(Chain, T9Reg, Load, InFlag);
+ } else
+ /// Indirect call
+ Chain = CurDAG->getCopyToReg(Chain, T9Reg, Callee, InFlag);
+
+ AddToISelQueue(Chain);
+
+ // Emit Jump and Link Register
+ SDNode *ResNode = CurDAG->getTargetNode(Mips::JALR, MVT::Other,
+ MVT::Flag, T9Reg, Chain);
+ Chain = SDOperand(ResNode, 0);
+ InFlag = SDOperand(ResNode, 1);
+ ReplaceUses(SDOperand(Node, 0), Chain);
+ ReplaceUses(SDOperand(Node, 1), InFlag);
+ return ResNode;
+ }
}
}
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