[mips] Continue splitting Instruction.Predicates into smaller lists and re-join them...

[oota-llvm.git] / lib / Target / Mips / MipsCondMov.td

diff --git a/lib/Target/Mips/MipsCondMov.td b/lib/Target/Mips/MipsCondMov.td
index 1758eb59d8cf5a002564df3df494abf065918a26..27c201716a691fb653889cb475ca321241185b95 100644 (file)
--- a/lib/Target/Mips/MipsCondMov.td
+++ b/lib/Target/Mips/MipsCondMov.td
@@ -141,14 +141,14 @@ let isCodeGenOnly = 1 in
 def MOVN_I64_S : CMov_I_F_FT<"movn.s", GPR64Opnd, FGR32Opnd, II_MOVN_S>,
                  CMov_I_F_FM<19, 16>, AdditionalRequires<[IsGP64bit]>;
 
-let AdditionalPredicates = [NotFP64bit] in {
+let FGRPredicates = [NotFP64bit] in {
   def MOVZ_I_D32 : MMRel, CMov_I_F_FT<"movz.d", GPR32Opnd, AFGR64Opnd,
                                       II_MOVZ_D>, CMov_I_F_FM<18, 17>;
   def MOVN_I_D32 : MMRel, CMov_I_F_FT<"movn.d", GPR32Opnd, AFGR64Opnd,
                                       II_MOVN_D>, CMov_I_F_FM<19, 17>;
 }
 
-let AdditionalPredicates = [IsFP64bit], DecoderNamespace = "Mips64" in {
+let FGRPredicates = [IsFP64bit], DecoderNamespace = "Mips64" in {
   def MOVZ_I_D64 : CMov_I_F_FT<"movz.d", GPR32Opnd, FGR64Opnd, II_MOVZ_D>,
                    CMov_I_F_FM<18, 17>;
   def MOVN_I_D64 : CMov_I_F_FT<"movn.d", GPR32Opnd, FGR64Opnd, II_MOVN_D>,
@@ -180,14 +180,14 @@ def MOVT_S : MMRel, CMov_F_F_FT<"movt.s", FGR32Opnd, II_MOVT_S, MipsCMovFP_T>,
 def MOVF_S : MMRel, CMov_F_F_FT<"movf.s", FGR32Opnd, II_MOVF_S, MipsCMovFP_F>,
              CMov_F_F_FM<16, 0>;
 
-let AdditionalPredicates = [NotFP64bit] in {
+let FGRPredicates = [NotFP64bit] in {
   def MOVT_D32 : MMRel, CMov_F_F_FT<"movt.d", AFGR64Opnd, II_MOVT_D,
                                     MipsCMovFP_T>, CMov_F_F_FM<17, 1>;
   def MOVF_D32 : MMRel, CMov_F_F_FT<"movf.d", AFGR64Opnd, II_MOVF_D,
                                     MipsCMovFP_F>, CMov_F_F_FM<17, 0>;
 }
 
-let AdditionalPredicates = [IsFP64bit], DecoderNamespace = "Mips64" in {
+let FGRPredicates = [IsFP64bit], DecoderNamespace = "Mips64" in {
   def MOVT_D64 : CMov_F_F_FT<"movt.d", FGR64Opnd, II_MOVT_D, MipsCMovFP_T>,
                  CMov_F_F_FM<17, 1>;
   def MOVF_D64 : CMov_F_F_FT<"movf.d", FGR64Opnd, II_MOVF_D, MipsCMovFP_F>,
@@ -198,7 +198,7 @@ let AdditionalPredicates = [IsFP64bit], DecoderNamespace = "Mips64" in {
 defm : MovzPats0<GPR32, GPR32, MOVZ_I_I, SLT, SLTu, SLTi, SLTiu>;
 defm : MovzPats1<GPR32, GPR32, MOVZ_I_I, XOR>;
 defm : MovzPats2<GPR32, GPR32, MOVZ_I_I, XORi>;
-let AdditionalPredicates = [IsGP64bit] in {
+let GPRPredicates = [IsGP64bit] in {
   defm : MovzPats0<GPR32, GPR64, MOVZ_I_I64, SLT, SLTu, SLTi, SLTiu>;
   defm : MovzPats0<GPR64, GPR32, MOVZ_I_I, SLT64, SLTu64, SLTi64,
                    SLTiu64>;
@@ -213,7 +213,7 @@ let AdditionalPredicates = [IsGP64bit] in {
 }
 
 defm : MovnPats<GPR32, GPR32, MOVN_I_I, XOR>;
-let AdditionalPredicates = [IsGP64bit] in {
+let GPRPredicates = [IsGP64bit] in {
   defm : MovnPats<GPR32, GPR64, MOVN_I_I64, XOR>;
   defm : MovnPats<GPR64, GPR32, MOVN_I64_I, XOR64>;
   defm : MovnPats<GPR64, GPR64, MOVN_I64_I64, XOR64>;
@@ -222,19 +222,18 @@ let AdditionalPredicates = [IsGP64bit] in {
 defm : MovzPats0<GPR32, FGR32, MOVZ_I_S, SLT, SLTu, SLTi, SLTiu>;
 defm : MovzPats1<GPR32, FGR32, MOVZ_I_S, XOR>;
 defm : MovnPats<GPR32, FGR32, MOVN_I_S, XOR>;
-let AdditionalPredicates = [IsGP64bit] in {
-  defm : MovzPats0<GPR64, FGR32, MOVZ_I_S, SLT64, SLTu64, SLTi64,
-                   SLTiu64>;
+let GPRPredicates = [IsGP64bit] in {
+  defm : MovzPats0<GPR64, FGR32, MOVZ_I_S, SLT64, SLTu64, SLTi64, SLTiu64>;
   defm : MovzPats1<GPR64, FGR32, MOVZ_I64_S, XOR64>;
   defm : MovnPats<GPR64, FGR32, MOVN_I64_S, XOR64>;
 }
 
-let AdditionalPredicates = [NotFP64bit] in {
+let FGRPredicates = [NotFP64bit] in {
   defm : MovzPats0<GPR32, AFGR64, MOVZ_I_D32, SLT, SLTu, SLTi, SLTiu>;
   defm : MovzPats1<GPR32, AFGR64, MOVZ_I_D32, XOR>;
   defm : MovnPats<GPR32, AFGR64, MOVN_I_D32, XOR>;
 }
-let AdditionalPredicates = [IsFP64bit] in {
+let FGRPredicates = [IsFP64bit] in {
   defm : MovzPats0<GPR32, FGR64, MOVZ_I_D64, SLT, SLTu, SLTi, SLTiu>;
   defm : MovzPats0<GPR64, FGR64, MOVZ_I_D64, SLT64, SLTu64, SLTi64,
                    SLTiu64>;