//
//===----------------------------------------------------------------------===//
+class DDIV_ENC : SPECIAL_3R_FM<0b00010, 0b011110>;
+class DDIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011111>;
+class DMOD_ENC : SPECIAL_3R_FM<0b00011, 0b011110>;
+class DMODU_ENC : SPECIAL_3R_FM<0b00011, 0b011111>;
class DMUH_ENC : SPECIAL_3R_FM<0b00011, 0b111000>;
class DMUHU_ENC : SPECIAL_3R_FM<0b00011, 0b111001>;
class DMUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b111000>;
//
//===----------------------------------------------------------------------===//
+class DDIV_DESC : DIVMOD_DESC_BASE<"ddiv", GPR64Opnd>;
+class DDIVU_DESC : DIVMOD_DESC_BASE<"ddivu", GPR64Opnd>;
+class DMOD_DESC : DIVMOD_DESC_BASE<"dmod", GPR64Opnd>;
+class DMODU_DESC : DIVMOD_DESC_BASE<"dmodu", GPR64Opnd>;
class DMUH_DESC : MUL_R6_DESC_BASE<"dmuh", GPR64Opnd>;
class DMUHU_DESC : MUL_R6_DESC_BASE<"dmuhu", GPR64Opnd>;
class DMUL_R6_DESC : MUL_R6_DESC_BASE<"dmul", GPR64Opnd>;
def DATI;
def DAUI;
def DBITSWAP;
-def DDIV;
-def DDIVU;
+def DDIV : DDIV_ENC, DDIV_DESC, ISA_MIPS64R6;
+def DDIVU : DDIVU_ENC, DDIVU_DESC, ISA_MIPS64R6;
// def DLSA; // See MSA
-def DMOD;
-def DMODU;
+def DMOD : DMOD_ENC, DMOD_DESC, ISA_MIPS64R6;
+def DMODU : DMODU_ENC, DMODU_DESC, ISA_MIPS64R6;
def DMUH: DMUH_ENC, DMUH_DESC, ISA_MIPS64R6;
def DMUHU: DMUHU_ENC, DMUHU_DESC, ISA_MIPS64R6;
def DMUL_R6: DMUL_R6_ENC, DMUL_R6_DESC, ISA_MIPS64R6;