remove blanks, and some code format

[oota-llvm.git] / lib / Target / Mips / Mips64InstrInfo.td

diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td
index fb1cea58fd0817ddf197e56ee5e1f7c3a2aef2b6..16aec6237ffb19051e4cdef7d054c3414254ab2e 100644 (file)
--- a/lib/Target/Mips/Mips64InstrInfo.td
+++ b/lib/Target/Mips/Mips64InstrInfo.td
@@ -31,19 +31,6 @@ def Subtract32 : SDNodeXForm<imm, [{
 // shamt must fit in 6 bits.
 def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>;
 
-// Is a 32-bit int.
-def immSExt32 : ImmLeaf<i64, [{return isInt<32>(Imm);}]>;
-
-// Transformation Function - get the higher 16 bits.
-def HIGHER : SDNodeXForm<imm, [{
-  return getImm(N, (N->getZExtValue() >> 32) & 0xFFFF);
-}]>;
-
-// Transformation Function - get the highest 16 bits.
-def HIGHEST : SDNodeXForm<imm, [{
-  return getImm(N, (N->getZExtValue() >> 48) & 0xFFFF);
-}]>;
-
 //===----------------------------------------------------------------------===//
 // Instructions specific format
 //===----------------------------------------------------------------------===//
@@ -121,7 +108,7 @@ let Predicates = [HasMips64r2] in {
 }
 
 /// Load and Store Instructions
-///  aligned 
+///  aligned
 defm LB64    : LoadM64<0x20, "lb",  sextloadi8>;
 defm LBu64   : LoadM64<0x24, "lbu", zextloadi8>;
 defm LH64    : LoadM64<0x21, "lh",  sextloadi16_a>;
@@ -178,6 +165,10 @@ def MTLO64 : MoveToLOHI<0x13, "mtlo", CPU64Regs, [LO64]>;
 def MFHI64 : MoveFromLOHI<0x10, "mfhi", CPU64Regs, [HI64]>;
 def MFLO64 : MoveFromLOHI<0x12, "mflo", CPU64Regs, [LO64]>;
 
+/// Sign Ext In Register Instructions.
+def SEB64 : SignExtInReg<0x10, "seb", i8, CPU64Regs>;
+def SEH64 : SignExtInReg<0x18, "seh", i16, CPU64Regs>;
+
 /// Count Leading
 def DCLZ : CountLeading0<0x24, "dclz", CPU64Regs>;
 def DCLO : CountLeading1<0x25, "dclo", CPU64Regs>;
@@ -209,24 +200,6 @@ def SLL64_64 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPU64Regs:$rt),
 //  Arbitrary patterns that map to one or more instructions
 //===----------------------------------------------------------------------===//
 
-// Small immediates
-def : Pat<(i64 immSExt16:$in),
-          (DADDiu ZERO_64, imm:$in)>;
-def : Pat<(i64 immZExt16:$in),
-          (ORi64 ZERO_64, imm:$in)>;
-def : Pat<(i64 immLow16Zero:$in),
-          (LUi64 (HI16 imm:$in))>;
-
-// 32-bit immediates
-def : Pat<(i64 immSExt32:$imm),
-          (ORi64 (LUi64 (HI16 imm:$imm)), (LO16 imm:$imm))>;
-
-// Arbitrary immediates
-def : Pat<(i64 imm:$imm),
-          (ORi64 (DSLL (ORi64 (DSLL (ORi64 (LUi64 (HIGHEST imm:$imm)),
-           (HIGHER imm:$imm)), 16), (HI16 imm:$imm)), 16),
-           (LO16 imm:$imm))>;
-
 // extended loads
 let Predicates = [NotN64] in {
   def : Pat<(i64 (extloadi1  addr:$src)), (LB64 addr:$src)>;
@@ -271,12 +244,12 @@ def : Pat<(add CPU64Regs:$hi, (MipsLo tconstpool:$lo)),
 def : Pat<(add CPU64Regs:$hi, (MipsLo tglobaltlsaddr:$lo)),
           (DADDiu CPU64Regs:$hi, tglobaltlsaddr:$lo)>;
 
-def : WrapperPat<tglobaladdr, DADDiu, GP_64>;
-def : WrapperPat<tconstpool, DADDiu, GP_64>;
-def : WrapperPat<texternalsym, DADDiu, GP_64>;
-def : WrapperPat<tblockaddress, DADDiu, GP_64>;
-def : WrapperPat<tjumptable, DADDiu, GP_64>;
-def : WrapperPat<tglobaltlsaddr, DADDiu, GP_64>;
+def : WrapperPat<tglobaladdr, DADDiu, CPU64Regs>;
+def : WrapperPat<tconstpool, DADDiu, CPU64Regs>;
+def : WrapperPat<texternalsym, DADDiu, CPU64Regs>;
+def : WrapperPat<tblockaddress, DADDiu, CPU64Regs>;
+def : WrapperPat<tjumptable, DADDiu, CPU64Regs>;
+def : WrapperPat<tglobaltlsaddr, DADDiu, CPU64Regs>;
 
 defm : BrcondPats<CPU64Regs, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64,
                   ZERO_64>;
@@ -294,7 +267,7 @@ def : Pat<(MipsDynAlloc addr:$f), (DynAlloc64 addr:$f)>, Requires<[IsN64]>;
 // truncate
 def : Pat<(i32 (trunc CPU64Regs:$src)),
           (SLL (EXTRACT_SUBREG CPU64Regs:$src, sub_32), 0)>, Requires<[IsN64]>;
- 
+
 // 32-to-64-bit extension
 def : Pat<(i64 (anyext CPURegs:$src)), (SLL64_32 CPURegs:$src)>;
 def : Pat<(i64 (zext CPURegs:$src)), (DSRL (DSLL64_32 CPURegs:$src), 32)>;