[X86][AVX] Only shuffle the lower half of vectors if the upper half is undefined

[oota-llvm.git] / lib / Target / Mips / Mips16InstrInfo.cpp

diff --git a/lib/Target/Mips/Mips16InstrInfo.cpp b/lib/Target/Mips/Mips16InstrInfo.cpp
index c7c87d38db944b48a50843a32cfdd845ffd164b1..da8ada4e53917f793257ee94a942f5564d0c7b16 100644 (file)
--- a/lib/Target/Mips/Mips16InstrInfo.cpp
+++ b/lib/Target/Mips/Mips16InstrInfo.cpp
@@ -193,13 +193,13 @@ static void addSaveRestoreRegs(MachineInstrBuilder &MIB,
   }
 }
 // Adjust SP by FrameSize bytes. Save RA, S0, S1
-void Mips16InstrInfo::makeFrame(unsigned SP, int64_t FrameSize,\r
-                                MachineBasicBlock &MBB,\r
-                                MachineBasicBlock::iterator I) const {\r
-  DebugLoc DL;\r
-  MachineFunction &MF = *MBB.getParent();\r
-  MachineFrameInfo *MFI    = MF.getFrameInfo();\r
-  const BitVector Reserved = RI.getReservedRegs(MF);\r
+void Mips16InstrInfo::makeFrame(unsigned SP, int64_t FrameSize,
+                                MachineBasicBlock &MBB,
+                                MachineBasicBlock::iterator I) const {
+  DebugLoc DL;
+  MachineFunction &MF = *MBB.getParent();
+  MachineFrameInfo *MFI    = MF.getFrameInfo();
+  const BitVector Reserved = RI.getReservedRegs(MF);
   bool SaveS2 = Reserved[Mips::S2];
   MachineInstrBuilder MIB;
   unsigned Opc = ((FrameSize <= 128) && !SaveS2)? Mips::Save16:Mips::SaveX16;
@@ -260,13 +260,13 @@ void Mips16InstrInfo::restoreFrame(unsigned SP, int64_t FrameSize,
 // This is clearly safe at prologue and epilogue.
 //
 void Mips16InstrInfo::adjustStackPtrBig(unsigned SP, int64_t Amount,
-                                        MachineBasicBlock &MBB,\r
-                                        MachineBasicBlock::iterator I,\r
-                                        unsigned Reg1, unsigned Reg2) const {\r
-  DebugLoc DL;\r
-  //\r
-  // li reg1, constant\r
-  // move reg2, sp\r
+                                        MachineBasicBlock &MBB,
+                                        MachineBasicBlock::iterator I,
+                                        unsigned Reg1, unsigned Reg2) const {
+  DebugLoc DL;
+  //
+  // li reg1, constant
+  // move reg2, sp
   // add reg1, reg1, reg2
   // move sp, reg1
   //
@@ -443,13 +443,13 @@ const MCInstrDesc &Mips16InstrInfo::AddiuSpImm(int64_t Imm) const {
   else
     return get(Mips::AddiuSpImmX16);
 }
-\r
-void Mips16InstrInfo::BuildAddiuSpImm\r
-  (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const {\r
-  DebugLoc DL;\r
-  BuildMI(MBB, I, DL, AddiuSpImm(Imm)).addImm(Imm);\r
-}\r
-\r
+
+void Mips16InstrInfo::BuildAddiuSpImm
+  (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const {
+  DebugLoc DL;
+  BuildMI(MBB, I, DL, AddiuSpImm(Imm)).addImm(Imm);
+}
+
 const MipsInstrInfo *llvm::createMips16InstrInfo(const MipsSubtarget &STI) {
   return new Mips16InstrInfo(STI);
 }